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esd/common/fpga.c: fix indentation.

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-03-09 10:50:41 +01:00
parent cc3843e364
commit 2b3e7e61d6
1 changed files with 161 additions and 171 deletions
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96
board/esd/common/fpga.c
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@ -97,6 +97,7 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
int i, index, len; int i, index, len;
int count; int count;
unsigned char b; unsigned char b;
#ifdef CFG_FPGA_SPARTAN2 #ifdef CFG_FPGA_SPARTAN2
int j; int j;
#else #else
@ -105,8 +106,7 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
/* display infos on fpgaimage */ /* display infos on fpgaimage */
index = 15; index = 15;
for (i=0; i<4; i++) for (i = 0; i < 4; i++) {
{
len = fpgadata[index]; len = fpgadata[index];
DBG ("FPGA: %s\n", &(fpgadata[index + 1])); DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
index += len + 3; index += len + 3;
@ -114,19 +114,19 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
#ifdef CFG_FPGA_SPARTAN2 #ifdef CFG_FPGA_SPARTAN2
/* search for preamble 0xFFFFFFFF */ /* search for preamble 0xFFFFFFFF */
while (1) while (1) {
{ if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && && (fpgadata[index + 2] == 0xff)
(fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) && (fpgadata[index + 3] == 0xff))
break; /* preamble found */ break; /* preamble found */
else else
index++; index++;
} }
#else #else
/* search for preamble 0xFF2X */ /* search for preamble 0xFF2X */
for (index = 0; index < size-1 ; index++) for (index = 0; index < size - 1; index++) {
{ if ((fpgadata[index] == 0xff)
if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30)) && ((fpgadata[index + 1] & 0xf0) == 0x30))
break; break;
} }
index += 2; index += 2;
@ -154,12 +154,10 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
/* Wait for FPGA init line low */ /* Wait for FPGA init line low */
count = 0; count = 0;
while (FPGA_INIT_STATE) while (FPGA_INIT_STATE) {
{
udelay (1000); /* wait 1ms */ udelay (1000); /* wait 1ms */
/* Check for timeout - 100us max, so use 3ms */ /* Check for timeout - 100us max, so use 3ms */
if (count++ > 3) if (count++ > 3) {
{
DBG ("FPGA: Booting failed!\n"); DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_LOW; return ERROR_FPGA_PRG_INIT_LOW;
} }
@ -173,12 +171,10 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
/* Wait for FPGA end of init period . */ /* Wait for FPGA end of init period . */
count = 0; count = 0;
while (!(FPGA_INIT_STATE)) while (!(FPGA_INIT_STATE)) {
{
udelay (1000); /* wait 1ms */ udelay (1000); /* wait 1ms */
/* Check for timeout */ /* Check for timeout */
if (count++ > 3) if (count++ > 3) {
{
DBG ("FPGA: Booting failed!\n"); DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_INIT_HIGH; return ERROR_FPGA_PRG_INIT_HIGH;
} }
@ -194,17 +190,12 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
/* /*
* Load uncompressed image into fpga * Load uncompressed image into fpga
*/ */
for (i=index; i<size; i++) for (i = index; i < size; i++) {
{
b = fpgadata[i]; b = fpgadata[i];
for (j=0; j<8; j++) for (j = 0; j < 8; j++) {
{ if ((b & 0x80) == 0x80) {
if ((b & 0x80) == 0x80)
{
FPGA_WRITE_1; FPGA_WRITE_1;
} } else {
else
{
FPGA_WRITE_0; FPGA_WRITE_0;
} }
b <<= 1; b <<= 1;
@ -212,10 +203,22 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
} }
#else #else
/* send 0xff 0x20 */ /* send 0xff 0x20 */
FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0; FPGA_WRITE_1;
FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_1;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
FPGA_WRITE_0;
/* /*
** Bit_DeCompression ** Bit_DeCompression
@ -225,34 +228,23 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
** 255 : '1' ** 255 : '1'
*/ */
for (i=index; i<size; i++) for (i = index; i < size; i++) {
{
b = fpgadata[i]; b = fpgadata[i];
if ((b >= 1) && (b <= MAX_ONES)) if ((b >= 1) && (b <= MAX_ONES)) {
{ for (bit = 0; bit < b; bit++) {
for(bit=0; bit<b; bit++)
{
FPGA_WRITE_1; FPGA_WRITE_1;
} }
FPGA_WRITE_0; FPGA_WRITE_0;
} } else if (b == (MAX_ONES + 1)) {
else if (b == (MAX_ONES+1)) for (bit = 1; bit < b; bit++) {
{
for(bit=1; bit<b; bit++)
{
FPGA_WRITE_1; FPGA_WRITE_1;
} }
} } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
else if ((b >= (MAX_ONES+2)) && (b <= 254)) for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
{
for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
{
FPGA_WRITE_0; FPGA_WRITE_0;
} }
FPGA_WRITE_1; FPGA_WRITE_1;
} } else if (b == 255) {
else if (b == 255)
{
FPGA_WRITE_1; FPGA_WRITE_1;
} }
} }
@ -267,12 +259,10 @@ static int fpga_boot(const unsigned char *fpgadata, int size)
/* Wait for FPGA end of programming period . */ /* Wait for FPGA end of programming period . */
count = 0; count = 0;
while (!(FPGA_DONE_STATE)) while (!(FPGA_DONE_STATE)) {
{
udelay (1000); /* wait 1ms */ udelay (1000); /* wait 1ms */
/* Check for timeout */ /* Check for timeout */
if (count++ > 3) if (count++ > 3) {
{
DBG ("FPGA: Booting failed!\n"); DBG ("FPGA: Booting failed!\n");
return ERROR_FPGA_PRG_DONE; return ERROR_FPGA_PRG_DONE;
} }