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fsl: improve the PIXIS code and fix a few bugs

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Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx
boards.  This makes the code easier to read and more flexible.

Delete pixis.h, because none of the exported functions were actually being
used by any other file.  Make all of the functions in pixis.c 'static'.
Remove "#include pixis.h" from every file that has it.

Remove some unnecessary #includes.

Make 'pixis_base' into a macro, so that we don't need to define it in every
function.

Add "while(1);" loops at the end of functions that reset the board, so that
execution doesn't continue while the reset is in progress.

Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where
appropriate.

Replace ulong/uint with their spelled-out equivalents.  Remove unnecessary
typecasts, changing the types of some variables if necessary.

Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make
it easier for specific boards to support variations in the PIXIS registers
sets.  No current boards appears to need this feature.

Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD.
Apparently, "pixis_reset altbank" has never worked on this board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi 2010-03-31 17:44:13 -05:00 committed by Kumar Gala
parent ff8473e90a
commit 2feb4af001
11 changed files with 127 additions and 170 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

254
board/freescale/common/pixis.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright 2006 Freescale Semiconductor * Copyright 2006,2010 Freescale Semiconductor
* Jeff Brown * Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
* *
@ -24,33 +24,26 @@
#include <common.h> #include <common.h>
#include <command.h> #include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <asm/io.h> #include <asm/io.h>
#include "pixis.h" #define pixis_base (u8 *)PIXIS_BASE
static ulong strfractoint(uchar *strptr);
/* /*
* Simple board reset. * Simple board reset.
*/ */
void pixis_reset(void) void pixis_reset(void)
{ {
u8 *pixis_base = (u8 *)PIXIS_BASE;
out_8(pixis_base + PIXIS_RST, 0); out_8(pixis_base + PIXIS_RST, 0);
}
while (1);
}
/* /*
* Per table 27, page 58 of MPC8641HPCN spec. * Per table 27, page 58 of MPC8641HPCN spec.
*/ */
int set_px_sysclk(ulong sysclk) static int set_px_sysclk(unsigned long sysclk)
{ {
u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (sysclk) { switch (sysclk) {
case 33: case 33:
@ -117,13 +110,13 @@ int set_px_sysclk(ulong sysclk)
return 1; return 1;
} }
/* Set the CFG_SYSPLL bits
int set_px_mpxpll(ulong mpxpll) *
* This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
* read_from_px_regs() is called.
*/
static int set_px_mpxpll(unsigned long mpxpll)
{ {
u8 tmp;
u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch (mpxpll) { switch (mpxpll) {
case 2: case 2:
case 4: case 4:
@ -133,28 +126,19 @@ int set_px_mpxpll(ulong mpxpll)
case 12: case 12:
case 14: case 14:
case 16: case 16:
val = (u8) mpxpll; clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
break; return 1;
default:
printf("Unsupported MPXPLL ratio.\n");
return 0;
} }
tmp = in_8(pixis_base + PIXIS_VSPEED1); printf("Unsupported MPXPLL ratio.\n");
tmp = (tmp & 0xF0) | (val & 0x0F); return 0;
out_8(pixis_base + PIXIS_VSPEED1, tmp);
return 1;
} }
static int set_px_corepll(unsigned long corepll)
int set_px_corepll(ulong corepll)
{ {
u8 tmp;
u8 val; u8 val;
u8 *pixis_base = (u8 *)PIXIS_BASE;
switch ((int)corepll) { switch (corepll) {
case 20: case 20:
val = 0x08; val = 0x08;
break; break;
@ -178,113 +162,132 @@ int set_px_corepll(ulong corepll)
return 0; return 0;
} }
tmp = in_8(pixis_base + PIXIS_VSPEED0); clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
tmp = (tmp & 0xE0) | (val & 0x1F);
out_8(pixis_base + PIXIS_VSPEED0, tmp);
return 1; return 1;
} }
#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
#endif
void read_from_px_regs(int set) /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or various other PIXIS registers to determine the values for COREPLL,
* MPXPLL, and SYSCLK.
*
* CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
* register that tells the pixis to use the various PIXIS register.
*/
static void read_from_px_regs(int set)
{ {
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
if (set) if (set)
tmp = tmp | mask; tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
else else
tmp = tmp & ~mask; tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN0, tmp); out_8(pixis_base + PIXIS_VCFGEN0, tmp);
} }
/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
* register that tells the pixis to use the PX_VBOOT[LBMAP] register.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
#endif
void read_from_px_regs_altbank(int set) /* Configure the source of the boot location
*
* The PIXIS can be programmed to look at either the on-board dip switches
* or the PX_VBOOT[LBMAP] register to determine where we should boot.
*
* If we want to boot from the alternate boot bank, we need to tell the PIXIS
* to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
*/
static void read_from_px_regs_altbank(int set)
{ {
u8 *pixis_base = (u8 *)PIXIS_BASE;
u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
if (set) if (set)
tmp = tmp | mask; tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
else else
tmp = tmp & ~mask; tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
out_8(pixis_base + PIXIS_VCFGEN1, tmp); out_8(pixis_base + PIXIS_VCFGEN1, tmp);
} }
/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
* tells the PIXIS what the alternate flash bank is.
*
* Note that it's not really a mask. It contains the actual LBMAP bits that
* must be set to select the alternate bank. This code assumes that the
* primary bank has these bits set to 0, and the alternate bank has these
* bits set to 1.
*/
#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40) #define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
#endif #endif
void clear_altbank(void) /* Tell the PIXIS to boot from the default flash bank
*
* Program the default flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void clear_altbank(void)
{ {
u8 tmp; clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
out_8(pixis_base + PIXIS_VBOOT, tmp);
} }
/* Tell the PIXIS to boot from the alternate flash bank
void set_altbank(void) *
* Program the alternate flash bank into the VBOOT register. This register is
* used only if PX_VCFGEN1[FLASH]=1.
*/
static void set_altbank(void)
{ {
u8 tmp; setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
u8 *pixis_base = (u8 *)PIXIS_BASE;
tmp = in_8(pixis_base + PIXIS_VBOOT);
tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
out_8(pixis_base + PIXIS_VBOOT, tmp);
} }
/* Reset the board with watchdog disabled.
void set_px_go(void) *
* This respects the altbank setting.
*/
static void set_px_go(void)
{ {
u8 tmp; /* Disable the VELA sequencer and watchdog */
u8 *pixis_base = (u8 *)PIXIS_BASE; clrbits_8(pixis_base + PIXIS_VCTL, 9);
tmp = in_8(pixis_base + PIXIS_VCTL); /* Reboot by starting the VELA sequencer */
tmp = tmp & 0x1E; /* clear GO bit */ setbits_8(pixis_base + PIXIS_VCTL, 0x1);
out_8(pixis_base + PIXIS_VCTL, tmp);
tmp = in_8(pixis_base + PIXIS_VCTL); while (1);
tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
out_8(pixis_base + PIXIS_VCTL, tmp);
} }
/* Reset the board with watchdog enabled.
void set_px_go_with_watchdog(void) *
* This respects the altbank setting.
*/
static void set_px_go_with_watchdog(void)
{ {
u8 tmp; /* Disable the VELA sequencer */
u8 *pixis_base = (u8 *)PIXIS_BASE; clrbits_8(pixis_base + PIXIS_VCTL, 1);
tmp = in_8(pixis_base + PIXIS_VCTL); /* Enable the watchdog and reboot by starting the VELA sequencer */
tmp = tmp & 0x1E; setbits_8(pixis_base + PIXIS_VCTL, 0x9);
out_8(pixis_base + PIXIS_VCTL, tmp);
tmp = in_8(pixis_base + PIXIS_VCTL); while (1);
tmp = tmp | 0x09;
out_8(pixis_base + PIXIS_VCTL, tmp);
} }
/* Disable the watchdog
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, *
int flag, int argc, char *argv[]) */
static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char *argv[])
{ {
u8 tmp; /* Disable the VELA sequencer and the watchdog */
u8 *pixis_base = (u8 *)PIXIS_BASE; clrbits_8(pixis_base + PIXIS_VCTL, 9);
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp = tmp & 0x1E;
out_8(pixis_base + PIXIS_VCTL, tmp);
/* setting VCTL[WDEN] to 0 to disable watch dog */
tmp = in_8(pixis_base + PIXIS_VCTL);
tmp &= ~0x08;
out_8(pixis_base + PIXIS_VCTL, tmp);
return 0; return 0;
} }
@ -296,16 +299,17 @@ U_BOOT_CMD(
); );
#ifdef CONFIG_PIXIS_SGMII_CMD #ifdef CONFIG_PIXIS_SGMII_CMD
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* Enable or disable SGMII mode for a TSEC
*/
static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
int which_tsec = -1; int which_tsec = -1;
u8 *pixis_base = (u8 *)PIXIS_BASE; unsigned char mask;
uchar mask; unsigned char switch_mask;
uchar switch_mask;
if (argc > 2) if ((argc > 2) && (strcmp(argv[1], "all") != 0))
if (strcmp(argv[1], "all") != 0) which_tsec = simple_strtoul(argv[1], NULL, 0);
which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) { switch (which_tsec) {
#ifdef CONFIG_TSEC1 #ifdef CONFIG_TSEC1
@ -363,6 +367,7 @@ U_BOOT_CMD(
" off - disables SGMII\n" " off - disables SGMII\n"
" switch - use switch settings" " switch - use switch settings"
); );
#endif #endif
/* /*
@ -371,14 +376,13 @@ U_BOOT_CMD(
* FPGA register values. * FPGA register values.
* input: strptr i.e. argv[2] * input: strptr i.e. argv[2]
*/ */
static unsigned long strfractoint(char *strptr)
static ulong strfractoint(uchar *strptr)
{ {
int i, j, retval; int i, j;
int mulconst; int mulconst;
int intarr_len = 0, decarr_len = 0, no_dec = 0; int intarr_len, no_dec = 0;
ulong intval = 0, decval = 0; unsigned long intval = 0, decval = 0;
uchar intarr[3], decarr[3]; char intarr[3], decarr[3];
/* Assign the integer part to intarr[] /* Assign the integer part to intarr[]
* If there is no decimal point i.e. * If there is no decimal point i.e.
@ -412,26 +416,21 @@ static ulong strfractoint(uchar *strptr)
j++; j++;
} }
decarr_len = j;
decarr[j] = '\0'; decarr[j] = '\0';
mulconst = 1; mulconst = 1;
for (i = 0; i < decarr_len; i++) for (i = 0; i < j; i++)
mulconst *= 10; mulconst *= 10;
decval = simple_strtoul((char *)decarr, NULL, 10); decval = simple_strtoul(decarr, NULL, 10);
} }
intval = simple_strtoul((char *)intarr, NULL, 10); intval = simple_strtoul(intarr, NULL, 10);
intval = intval * mulconst; intval = intval * mulconst;
retval = intval + decval; return intval + decval;
return retval;
} }
static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
unsigned int i; unsigned int i;
char *p_cf = NULL; char *p_cf = NULL;
@ -440,7 +439,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *p_cf_mpxpll = NULL; char *p_cf_mpxpll = NULL;
char *p_altbank = NULL; char *p_altbank = NULL;
char *p_wd = NULL; char *p_wd = NULL;
unsigned int unknown_param = 0; int unknown_param = 0;
/* /*
* No args is a simple reset request. * No args is a simple reset request.
@ -493,9 +492,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/ */
read_from_px_regs(0); read_from_px_regs(0);
if (p_altbank) { if (p_altbank)
read_from_px_regs_altbank(0); read_from_px_regs_altbank(0);
}
clear_altbank(); clear_altbank();
/* /*
@ -507,7 +506,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
unsigned long mpxpll; unsigned long mpxpll;
sysclk = simple_strtoul(p_cf_sysclk, NULL, 10); sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
corepll = strfractoint((uchar *) p_cf_corepll); corepll = strfractoint(p_cf_corepll);
mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10); mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
if (!(set_px_sysclk(sysclk) if (!(set_px_sysclk(sysclk)
@ -536,11 +535,10 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* /*
* Reset with watchdog specified. * Reset with watchdog specified.
*/ */
if (p_wd) { if (p_wd)
set_px_go_with_watchdog(); set_px_go_with_watchdog();
} else { else
set_px_go(); set_px_go();
}
/* /*
* Shouldn't be reached. * Shouldn't be reached.

31
board/freescale/common/pixis.h
View File

@ -1,31 +0,0 @@
/*
* Copyright 2006 Freescale Semiconductor
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
extern void pixis_reset(void);
extern int set_px_sysclk(ulong sysclk);
extern int set_px_mpxpll(ulong mpxpll);
extern int set_px_corepll(ulong corepll);
extern void read_from_px_regs(int set);
extern void read_from_px_regs_altbank(int set);
extern void set_altbank(void);
extern void set_px_go(void);
extern void set_px_go_with_watchdog(void);

1
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -39,7 +39,6 @@
#include <netdev.h> #include <netdev.h>
#include <sata.h> #include <sata.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h" #include "../common/sgmii_riser.h"
phys_size_t fixed_sdram(void); phys_size_t fixed_sdram(void);

1
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -35,7 +35,6 @@
#include <tsec.h> #include <tsec.h>
#include <netdev.h> #include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h" #include "../common/sgmii_riser.h"
int checkboard (void) int checkboard (void)

1
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -36,7 +36,6 @@
#include <tsec.h> #include <tsec.h>
#include <netdev.h> #include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h" #include "../common/sgmii_riser.h"
long int fixed_sdram(void); long int fixed_sdram(void);

2
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View File

@ -34,8 +34,6 @@
#include <spd_sdram.h> #include <spd_sdram.h>
#include <netdev.h> #include <netdev.h>
#include "../common/pixis.h"
void sdram_init(void); void sdram_init(void);
phys_size_t fixed_sdram(void); phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void); void mpc8610hpcd_diu_init(void);

1
board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
View File

@ -29,7 +29,6 @@
#ifdef CONFIG_FSL_DIU_FB #ifdef CONFIG_FSL_DIU_FB
#include "../common/pixis.h"
#include "../common/fsl_diu_fb.h" #include "../common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

2
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -31,8 +31,6 @@
#include <fdt_support.h> #include <fdt_support.h>
#include <netdev.h> #include <netdev.h>
#include "../common/pixis.h"
phys_size_t fixed_sdram(void); phys_size_t fixed_sdram(void);
int board_early_init_f(void) int board_early_init_f(void)

1
board/freescale/p2020ds/p2020ds.c
View File

@ -38,7 +38,6 @@
#include <asm/mp.h> #include <asm/mp.h>
#include <netdev.h> #include <netdev.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h" #include "../common/sgmii_riser.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;

1
cpu/mpc512x/diu.c
View File

@ -27,7 +27,6 @@
#include <command.h> #include <command.h>
#include <asm/io.h> #include <asm/io.h>
#include "../../board/freescale/common/pixis.h"
#include "../../board/freescale/common/fsl_diu_fb.h" #include "../../board/freescale/common/fsl_diu_fb.h"
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)

2
include/configs/MPC8610HPCD.h
View File

@ -177,7 +177,7 @@
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/ #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */