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ARMV7: S5P: rename from s5pc1xx to s5p

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Because of these are common files around s5p Socs, rename from s5pc1xx to s5p.
And getting cpu_id is SoC specific, so move to SoC's header file.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Minkyu Kang 2010-08-19 20:41:50 +09:00
parent 852bd07c80
commit 37168dab52
6 changed files with 28 additions and 22 deletions
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11
arch/arm/cpu/armv7/s5p-common/cpu_info.c
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@ -25,15 +25,14 @@
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
/* Default is s5pc100 */ /* Default is s5pc100 */
unsigned int s5pc1xx_cpu_id = 0xC100; unsigned int s5p_cpu_id = 0xC100;
#ifdef CONFIG_ARCH_CPU_INIT #ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
s5pc1xx_cpu_id = readl(samsung_get_base_pro_id()); s5p_set_cpu_id();
s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12);
s5pc1xx_clock_init(); s5p_clock_init();
return 0; return 0;
} }
@ -41,7 +40,7 @@ int arch_cpu_init(void)
u32 get_device_type(void) u32 get_device_type(void)
{ {
return s5pc1xx_cpu_id; return s5p_cpu_id;
} }
#ifdef CONFIG_DISPLAY_CPUINFO #ifdef CONFIG_DISPLAY_CPUINFO
@ -50,7 +49,7 @@ int print_cpuinfo(void)
char buf[32]; char buf[32];
printf("CPU:\tS5P%X@%sMHz\n", printf("CPU:\tS5P%X@%sMHz\n",
s5pc1xx_cpu_id, strmhz(buf, get_arm_clk())); s5p_cpu_id, strmhz(buf, get_arm_clk()));
return 0; return 0;
} }

16
arch/arm/cpu/armv7/s5p-common/timer.c
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@ -44,14 +44,14 @@ static unsigned long long timestamp; /* Monotonic incrementing timer */
static unsigned long lastdec; /* Last decremneter snapshot */ static unsigned long lastdec; /* Last decremneter snapshot */
/* macro to read the 16 bit timer */ /* macro to read the 16 bit timer */
static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void) static inline struct s5p_timer *s5p_get_base_timer(void)
{ {
return (struct s5pc1xx_timer *)samsung_get_base_timer(); return (struct s5p_timer *)samsung_get_base_timer();
} }
int timer_init(void) int timer_init(void)
{ {
struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); struct s5p_timer *const timer = s5p_get_base_timer();
u32 val; u32 val;
/* /*
@ -80,13 +80,13 @@ int timer_init(void)
lastdec = count_value; lastdec = count_value;
val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) | val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) |
S5PC1XX_TCON4_AUTO_RELOAD; TCON4_AUTO_RELOAD;
/* auto reload & manual update */ /* auto reload & manual update */
writel(val | S5PC1XX_TCON4_UPDATE, &timer->tcon); writel(val | TCON4_UPDATE, &timer->tcon);
/* start PWM timer 4 */ /* start PWM timer 4 */
writel(val | S5PC1XX_TCON4_START, &timer->tcon); writel(val | TCON4_START, &timer->tcon);
timestamp = 0; timestamp = 0;
@ -151,7 +151,7 @@ void __udelay(unsigned long usec)
void reset_timer_masked(void) void reset_timer_masked(void)
{ {
struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); struct s5p_timer *const timer = s5p_get_base_timer();
/* reset time */ /* reset time */
lastdec = readl(&timer->tcnto4); lastdec = readl(&timer->tcnto4);
@ -160,7 +160,7 @@ void reset_timer_masked(void)
unsigned long get_timer_masked(void) unsigned long get_timer_masked(void)
{ {
struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now = readl(&timer->tcnto4); unsigned long now = readl(&timer->tcnto4);
if (lastdec >= now) if (lastdec >= now)

2
arch/arm/cpu/armv7/s5pc1xx/clock.c
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@ -297,7 +297,7 @@ static unsigned long s5pc100_get_pclk(void)
return get_pclkd1(); return get_pclkd1();
} }
void s5pc1xx_clock_init(void) void s5p_clock_init(void)
{ {
if (cpu_is_s5pc110()) { if (cpu_is_s5pc110()) {
get_pll_clk = s5pc110_get_pll_clk; get_pll_clk = s5pc110_get_pll_clk;

2
arch/arm/include/asm/arch-s5pc1xx/clk.h
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@ -29,7 +29,7 @@
#define HPLL 3 #define HPLL 3
#define VPLL 4 #define VPLL 4
void s5pc1xx_clock_init(void); void s5p_clock_init(void);
extern unsigned long (*get_pll_clk)(int pllreg); extern unsigned long (*get_pll_clk)(int pllreg);
extern unsigned long (*get_arm_clk)(void); extern unsigned long (*get_arm_clk)(void);

11
arch/arm/include/asm/arch-s5pc1xx/cpu.h
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@ -57,13 +57,20 @@
#define S5PC110_VIC3_BASE 0xF2300000 #define S5PC110_VIC3_BASE 0xF2300000
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */ /* CPU detection macros */
extern unsigned int s5pc1xx_cpu_id; extern unsigned int s5p_cpu_id;
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC100_PRO_ID);
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}
#define IS_SAMSUNG_TYPE(type, id) \ #define IS_SAMSUNG_TYPE(type, id) \
static inline int cpu_is_##type(void) \ static inline int cpu_is_##type(void) \
{ \ { \
return s5pc1xx_cpu_id == id ? 1 : 0; \ return s5p_cpu_id == id ? 1 : 0; \
} }
IS_SAMSUNG_TYPE(s5pc100, 0xc100) IS_SAMSUNG_TYPE(s5pc100, 0xc100)

8
arch/arm/include/asm/arch-s5pc1xx/pwm.h
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@ -23,14 +23,14 @@
#define __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_
/* Interval mode(Auto Reload) of PWM Timer 4 */ /* Interval mode(Auto Reload) of PWM Timer 4 */
#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) #define TCON4_AUTO_RELOAD (1 << 22)
/* Update TCNTB4 */ /* Update TCNTB4 */
#define S5PC1XX_TCON4_UPDATE (1 << 21) #define TCON4_UPDATE (1 << 21)
/* start bit of PWM Timer 4 */ /* start bit of PWM Timer 4 */
#define S5PC1XX_TCON4_START (1 << 20) #define TCON4_START (1 << 20)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct s5pc1xx_timer { struct s5p_timer {
unsigned int tcfg0; unsigned int tcfg0;
unsigned int tcfg1; unsigned int tcfg1;
unsigned int tcon; unsigned int tcon;