minix/u-boot
1
0
Fork 0
mirror of https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git synced 2025-09-11 05:02:26 -04:00
Code Issues Packages Projects Releases Wiki Activity

Fix new found CFG_

Browse Source 
Also fix some minor typos.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2008-12-14 10:29:39 +01:00 committed by Wolfgang Denk
parent 0e0c862efe
commit 3aed3aa2c1
10 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
board/esd/pmc440/cmd_pmc440.c
View File

@ -364,7 +364,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
#endif #endif
/* /*
* gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
*/ */
param = base - (pram << 10); param = base - (pram << 10);
printf("PARAM: @%08x\n", param); printf("PARAM: @%08x\n", param);

2
board/xilinx/ppc405-generic/u-boot-ram.lds
View File

@ -127,7 +127,7 @@ SECTIONS
*(COMMON) *(COMMON)
} }
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ; _end = . ;
PROVIDE (end = .); PROVIDE (end = .);

2
board/xilinx/ppc405-generic/u-boot-rom.lds
View File

@ -137,7 +137,7 @@ SECTIONS
*(COMMON) *(COMMON)
} }
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ; _end = . ;
PROVIDE (end = .); PROVIDE (end = .);

2
cpu/arm926ejs/at91/usb.c
View File

@ -35,7 +35,7 @@ int usb_cpu_init(void)
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) defined(CONFIG_AT91SAM9263)
/* Enable PLLB */ /* Enable PLLB */
at91_sys_write(AT91_CKGR_PLLBR, CFG_AT91_PLLB); at91_sys_write(AT91_CKGR_PLLBR, CONFIG_SYS_AT91_PLLB);
while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
; ;
#endif #endif

2
cpu/mpc86xx/release.S
View File

@ -125,7 +125,7 @@ invl2:
mtspr HID0, r5 /* enable + invalidate */ mtspr HID0, r5 /* enable + invalidate */
mtspr HID0, r3 /* enable */ mtspr HID0, r3 /* enable */
sync sync
#ifdef CFG_L2 #ifdef CONFIG_SYS_L2
sync sync
lis r3, L2_ENABLE@h lis r3, L2_ENABLE@h
ori r3, r3, L2_ENABLE@l ori r3, r3, L2_ENABLE@l

6
include/configs/PMC440.h
View File

@ -219,7 +219,7 @@
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif #endif
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */ /* 440EPx errata CHIP 11 */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -490,8 +490,8 @@
#endif #endif
/* Memory Bank 1 (RESET) initialization */ /* Memory Bank 1 (RESET) initialization */
#define CFG_EBC_PB1AP 0x7f817200 //0x03017200 #define CONFIG_SYS_EBC_PB1AP 0x7f817200 //0x03017200
#define CFG_EBC_PB1CR (CFG_RESET_BASE | 0x1c000) #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
/* Memory Bank 4 (FPGA / 32Bit) initialization */ /* Memory Bank 4 (FPGA / 32Bit) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */

4
include/configs/afeb9260.h
View File

@ -29,7 +29,7 @@
/* ARM asynchronous clock */ /* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */ #define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */
#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */
@ -150,7 +150,7 @@
#define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CFG_LONGHELP 1 #define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1 #define CONFIG_CMDLINE_EDITING 1
#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) #define ROUND(A, B) (((A) + (B)) & ~((B) - 1))

2
include/configs/at91cap9adk.h
View File

@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */ #define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ #define CONFUG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */

2
include/configs/at91sam9260ek.h
View File

@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */ #define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */

2
include/configs/at91sam9263ek.h
View File

@ -32,7 +32,7 @@
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define AT91_MASTER_CLOCK 100000000 /* peripheral */ #define AT91_MASTER_CLOCK 100000000 /* peripheral */
#define AT91_CPU_CLOCK 200000000 /* cpu */ #define AT91_CPU_CLOCK 200000000 /* cpu */
#define CFG_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */ #define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */
#define AT91_SLOW_CLOCK 32768 /* slow clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */