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Patch by Wolter Kamphuis, 05 Dec 2003:

Browse Source 
Add support for SNMC's QS850/QS823/QS860T boards
This commit is contained in:
wdenk 2003-12-07 22:27:15 +00:00
parent b028f71513
commit 3bbc899fc0
21 changed files with 4601 additions and 280 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patch by Wolter Kamphuis, 05 Dec 2003:
Add support for SNMC's QS850/QS823/QS860T boards
* Patch by Yuli Barcohen, 3 Dec 2003:
"revive" U-Boot support for old Motorola MPC860ADS board

10
MAKEALL
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@ -43,11 +43,11 @@ LIST_8xx=" \
KUP4K LANTEC lwmon MBX \
MBX860T MHPC MPC86xADS MVS1 \
NETVIA NETVIA_V2 NX823 pcu_e \
R360MPI RBC823 rmu RPXClassic \
RPXlite RRvision SM850 SPD823TS \
svm_sc8xx SXNI855T TOP860 TQM823L \
TQM823L_LCD TQM850L TQM855L TQM860L \
v37 \
QS823 QS850 QS860T R360MPI \
RBC823 rmu RPXClassic RPXlite \
RRvision SM850 SPD823TS svm_sc8xx \
SXNI855T TOP860 TQM823L TQM823L_LCD \
TQM850L TQM855L TQM860L v37 \
"
#########################################################################

9
Makefile
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@ -376,6 +376,15 @@ NX823_config: unconfig
pcu_e_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens
QS850_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
QS823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc
QS860T_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc
R360MPI_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx r360mpi

9
README
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@ -221,6 +221,8 @@ Directory Hierarchy:
- board/pm826 Files specific to PM826 boards
- board/ppmc8260
Files specific to PPMC8260 boards
- board/snmc/qs850 Files specific to QS850/823 boards
- board/snmc/qs860t Files specific to QS860T boards
- board/rpxsuper
Files specific to RPXsuper boards
- board/rsdproto
@ -363,7 +365,8 @@ The following options need to be configured:
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900,
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS
CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850
CONFIG_QS823, CONFIG_QS860T
ARM based boards:
-----------------
@ -496,6 +499,7 @@ The following options need to be configured:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CFG_BAUDRATE_TABLE, see below.
CFG_BRGCLK_PRESCALE, baudrate prescale
- Interrupt driven serial port input:
CONFIG_SERIAL_SOFTWARE_FIFO
@ -1995,7 +1999,8 @@ configurations; the following names are supported:
ELPT860_config cmi_mpc5xx_config NETVIA_config
at91rm9200dk_config omap1510inn_config MPC8260ADS_config
omap1610inn_config ZPC1900_config MPC8540ADS_config
MPC8560ADS_config
MPC8560ADS_config QS850_config QS823_config
QS860T_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for

40
board/snmc/qs850/Makefile Normal file
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@ -0,0 +1,40 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

29
board/snmc/qs850/config.mk Normal file
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@ -0,0 +1,29 @@
#
# (C) Copyright 2002-2003
# Simple Network Magic Corporation, dnevil@snmc.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# QS850
# Start address of Bootloader in Flash
#
TEXT_BASE = 0xFFF00000

617
board/snmc/qs850/flash.c Normal file
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@ -0,0 +1,617 @@
/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/u-boot.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define FLASH_WORD_SIZE unsigned long
#define FLASH_ID_MASK 0xFFFFFFFF
/*-----------------------------------------------------------------------
* Functions
*/
/* stolen from esteem192e/flash.c */
ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
volatile FLASH_WORD_SIZE* flash_base;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here */
/* Test for 8M Flash first */
debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM);
flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM);
size_b0 = flash_get_size(flash_base, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
return 0;
}
if (size_b0 < 8*1024*1024) {
/* Not quite 8M, try 4M Flash base address */
debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM);
flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM);
size_b0 = flash_get_size(flash_base, &flash_info[0]);
}
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
return 0;
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets ((ulong)flash_base, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
size_b1 = 0 ;
flash_info[0].size = size_b0;
return(size_b0);
}
/* We have 2 banks */
size_b1 = flash_get_size(flash_base, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
}
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CFG_MONITOR_LEN,
base_b1+size_b1-1, &flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CFG_MONITOR_LEN,
base_b0+size_b0-1, &flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823.
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
long large_sect_size;
long small_sect_size;
/* set up sector start adress table */
large_sect_size = info->size / (info->sector_count - 8 + 1);
small_sect_size = large_sect_size / 8;
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
for (i = 0; i < 7; i++) {
info->start[i] = base;
base += small_sect_size;
}
for (; i < info->sector_count; i++) {
info->start[i] = base;
base += large_sect_size;
}
}
else
{
/* set sector offsets for top boot block type */
for (i = 0; i < (info->sector_count - 8); i++) {
info->start[i] = base;
base += large_sect_size;
}
for (; i < info->sector_count; i++) {
info->start[i] = base;
base += small_sect_size;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
uchar *boottype;
uchar botboot[]=", bottom boot sect)\n";
uchar topboot[]=", top boot sector)\n";
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
case FLASH_MAN_SST:
printf ("SST ");
break;
case FLASH_MAN_STM:
printf ("STM ");
break;
case FLASH_MAN_INTEL:
printf ("INTEL ");
break;
default:
printf ("Unknown Vendor ");
break;
}
if (info->flash_id & 0x0001 ) {
boottype = botboot;
} else {
boottype = topboot;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit%s",boottype);
break;
case FLASH_AM160T:
printf ("AM29LV160T (16 Mbit%s",boottype);
break;
case FLASH_AMDL163T:
printf ("AM29DL163T (16 Mbit%s",boottype);
break;
case FLASH_AMDL163B:
printf ("AM29DL163B (16 Mbit%s",boottype);
break;
case FLASH_AM320B:
printf ("AM29LV320B (32 Mbit%s",boottype);
break;
case FLASH_AM320T:
printf ("AM29LV320T (32 Mbit%s",boottype);
break;
case FLASH_AMDL323T:
printf ("AM29DL323T (32 Mbit%s",boottype);
break;
case FLASH_AMDL323B:
printf ("AM29DL323B (32 Mbit%s",boottype);
break;
case FLASH_AMDL322T:
printf ("AM29DL322T (32 Mbit%s",boottype);
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
{
short i;
ulong base = (ulong)addr;
FLASH_WORD_SIZE value;
/* Write auto select command: read Manufacturer ID */
/*
* Note: if it is an AMD flash and the word at addr[0000]
* is 0x00890089 this routine will think it is an Intel
* flash device and may(most likely) cause trouble.
*/
addr[0x0000] = 0x00900090;
if(addr[0x0000] != 0x00890089){
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00900090;
}
value = addr[0];
switch (value) {
case (AMD_MANUFACT & FLASH_ID_MASK):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & FLASH_ID_MASK):
info->flash_id = FLASH_MAN_FUJ;
break;
case (STM_MANUFACT & FLASH_ID_MASK):
info->flash_id = FLASH_MAN_STM;
break;
case (SST_MANUFACT & FLASH_ID_MASK):
info->flash_id = FLASH_MAN_SST;
break;
case (INTEL_MANUFACT & FLASH_ID_MASK):
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr[1]; /* device ID */
switch (value) {
case (AMD_ID_LV160T & FLASH_ID_MASK):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV160B & FLASH_ID_MASK):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_DL163T & FLASH_ID_MASK):
info->flash_id += FLASH_AMDL163T;
info->sector_count = 39;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_DL163B & FLASH_ID_MASK):
info->flash_id += FLASH_AMDL163B;
info->sector_count = 39;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_DL323T & FLASH_ID_MASK):
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00800000;
break; /* => 8 MB */
case (AMD_ID_DL323B & FLASH_ID_MASK):
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00800000;
break; /* => 8 MB */
case (AMD_ID_DL322T & FLASH_ID_MASK):
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00800000;
break; /* => 8 MB */
default:
/* FIXME*/
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
flash_get_offsets(base, info);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
info->protect[i] = addr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
*addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP) ) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00800080;
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
addr[0] = (0x00300030 & FLASH_ID_MASK);
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
(0x00800080&FLASH_ID_MASK) )
{
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile FLASH_WORD_SIZE *)info->start[0];
addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
printf (" done\n");
return rcode;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int l;
int i, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* AMD stuff */
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00A000A0;
*((vu_long *)dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

253
board/snmc/qs850/qs850.c Normal file
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@ -0,0 +1,253 @@
/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2002
* Simple Network Magic Corporation, dnevil@snmc.com
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/u-boot.h>
#include <commproc.h>
#include "mpc8xx.h"
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0f07cc04, 0x00adcc04, 0x00a74c00, 0x00bfcc04,
0x1fffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x0ff7fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0f07cc04, 0x0fafcc00, 0x01ad0c04, 0x1ff74c07,
0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x0ff7fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
0x00fffc00, 0x00fffc00, 0x0ffffc04, 0x0ff77c04,
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
0x1ffffc05, 0x1ffffc05, 0x1ffffc05, 0x1ffffc05,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0xffffcc04, 0x1ff5cc84, 0xffffcc04, 0xffffcc04,
0xffffcc84, 0xffffcc05, 0xffffcc04, 0xffffcc04,
0xffffcc04, 0xffffcc04, 0xffffcc04, 0xffffcc04,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x1ff74c04, 0xffffcc07, 0xffffaa34, 0x1fb54a37
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* Test ID string (QS850, QS823, ...)
*
* Always return 1
*/
int checkboard (void)
{
unsigned char *s, *e;
unsigned char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
s = (i>0) ? buf : NULL;
#ifdef CONFIG_QS850
if (!s || strncmp(s, "QS850", 5)) {
puts ("### No HW ID - assuming QS850");
#endif
#ifdef CONFIG_QS823
if (!s || strncmp(s, "QS823", 5)) {
puts ("### No HW ID - assuming QS823");
#endif
} else {
for (e=s; *e; ++e) {
if (*e == ' ')
break;
}
for ( ; s<e; ++s) {
putc (*s);
}
}
putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
/* SDRAM Mode Register Definitions */
/* Set SDRAM Burst Length to 4 (010) */
/* See Motorola MPC850 User Manual, Page 13-14 */
#define SDRAM_BURST_LENGTH (2)
/* Set Wrap Type to Sequential (0) */
/* See Motorola MPC850 User Manual, Page 13-14 */
#define SDRAM_WRAP_TYPE (0 << 3)
/* Set /CAS Latentcy to 2 clocks */
#define SDRAM_CAS_LATENTCY (2 << 4)
/* The Mode Register value must be shifted left by 2, since it is */
/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
#define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
#define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index)
/* Please note a value of zero = 16 loops */
#define REFRESH_INIT_LOOPS (0)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Prescaler for refresh
*/
memctl->memc_mptpr = CFG_MPTPR;
/*
* Map controller bank 1 to the SDRAM address
*/
memctl->memc_or1 = CFG_OR1;
memctl->memc_br1 = CFG_BR1;
udelay(1000);
/* perform SDRAM initialization sequence */
memctl->memc_mamr = CFG_16M_MAMR;
udelay(100);
/* Program the SDRAM's Mode Register */
memctl->memc_mar = SDRAM_MODE_REG;
/* Run the Prechard Pattern at 0x3C */
memctl->memc_mcr = UPMA_RUN(1,0x3c);
udelay(1);
/* Run the Refresh program residing at MAD index 0x30 */
/* This contains the CBR Refresh command with a loop */
/* The SDRAM must be refreshed at least 2 times */
/* Please note a value of zero = 16 loops */
memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
udelay(1);
/* Run the Exception program residing at MAD index 0x3E */
/* This contains the Write Mode Register command */
/* The Write Mode Register command uses the value written to MAR */
memctl->memc_mcr = UPMA_RUN(1,0x3e);
udelay (1000);
/*
* Check for 32M SDRAM Memory Size
*/
size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
(ulong *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
udelay (1000);
/*
* Check for 16M SDRAM Memory Size
*/
if (size != SDRAM_32M_MAX_SIZE) {
size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
(ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
}
udelay(10000);
return (size);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
}

141
board/snmc/qs850/u-boot.lds Normal file
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@ -0,0 +1,141 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

40
board/snmc/qs860t/Makefile Normal file
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@ -0,0 +1,40 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

29
board/snmc/qs860t/config.mk Normal file
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@ -0,0 +1,29 @@
#
# (C) Copyright 2002
# Simple Network Magic Corporation, dnevil@snmc.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# QS860T
# Start address of 512K Socketed Flash
#
TEXT_BASE = 0xFFF00000

1121
board/snmc/qs860t/flash.c Normal file
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File diff suppressed because it is too large Load Diff

259
board/snmc/qs860t/qs860t.c Normal file
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@ -0,0 +1,259 @@
/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2002
* Simple Network Magic Corporation, dnevil@snmc.com
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/u-boot.h>
#include <commproc.h>
#include "mpc8xx.h"
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* Test ID string (QS860T...)
*
* Always return 1
*/
int checkboard (void)
{
unsigned char *s, *e;
unsigned char buf[64];
int i;
i = getenv_r("serial#", buf, sizeof(buf));
s = (i>0) ? buf : NULL;
if (!s || strncmp(s, "QS860T", 6)) {
puts ("### No HW ID - assuming QS860T");
} else {
for (e=s; *e; ++e) {
if (*e == ' ')
break;
}
for ( ; s<e; ++s) {
putc (*s);
}
}
putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Prescaler for refresh
*/
memctl->memc_mptpr = 0x0400;
/*
* Map controller bank 2 to the SDRAM address
*/
memctl->memc_or2 = CFG_OR2;
memctl->memc_br2 = CFG_BR2;
udelay(200);
/* perform SDRAM initialization sequence */
memctl->memc_mbmr = CFG_16M_MBMR;
udelay(100);
memctl->memc_mar = 0x00000088;
memctl->memc_mcr = 0x80804105; /* run precharge pattern */
udelay(1);
/* Run two refresh cycles on SDRAM */
memctl->memc_mbmr = 0x18802118;
memctl->memc_mcr = 0x80804130;
memctl->memc_mbmr = 0x18802114;
memctl->memc_mcr = 0x80804106;
udelay (1000);
#if 0
/*
* Check for 64M SDRAM Memory Size
*/
size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
udelay (1000);
/*
* Check for 16M SDRAM Memory Size
*/
if (size != SDRAM_64M_MAX_SIZE) {
#endif
size = dram_size (CFG_16M_MBMR, (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
udelay (1000);
#if 0
}
memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
#endif
udelay(10000);
#if 0
/*
* Also, map other memory to correct position
*/
/*
* Map the 8M Intel Flash device to chip select 1
*/
memctl->memc_or1 = CFG_OR1;
memctl->memc_br1 = CFG_BR1;
/*
* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
* to chip select 3
*/
memctl->memc_or3 = CFG_OR3;
memctl->memc_br3 = CFG_BR3;
/*
* Map chip selects 4, 5, 6, & 7 for external expansion connector
*/
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;
memctl->memc_or5 = CFG_OR5;
memctl->memc_br5 = CFG_BR5;
memctl->memc_or6 = CFG_OR6;
memctl->memc_br6 = CFG_BR6;
memctl->memc_or7 = CFG_OR7;
memctl->memc_br7 = CFG_BR7;
#endif
return (size);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mbmr = mbmr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
}

141
board/snmc/qs860t/u-boot.lds Normal file
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@ -0,0 +1,141 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.ppcenv)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

561
cpu/mpc8xx/scc.c
View File

@ -140,42 +140,43 @@ static int scc_send(struct eth_device* dev, volatile void *packet, int length)
return i;
}
static int scc_recv(struct eth_device* dev)
static int scc_recv (struct eth_device *dev)
{
int length;
for (;;) {
/* section 16.9.23.2 */
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
for (;;) {
/* section 16.9.23.2 */
if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = rtx->rxbd[rxIdx].cbd_datlen;
length = rtx->rxbd[rxIdx].cbd_datlen;
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
#endif
} else {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[rxIdx], length - 4);
} else {
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[rxIdx], length - 4);
}
/* Give the buffer back to the SCC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
/* Give the buffer back to the SCC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
return length;
return length;
}
/**************************************************************
@ -184,366 +185,380 @@ static int scc_recv(struct eth_device* dev)
*
*************************************************************/
static int scc_init(struct eth_device* dev, bd_t *bis)
static int scc_init (struct eth_device *dev, bd_t * bis)
{
int i;
scc_enet_t *pram_ptr;
int i;
scc_enet_t *pram_ptr;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
#ifdef CONFIG_FADS
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN);
*((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif
pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]);
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
txIdx = 0;
rxIdx = 0;
txIdx = 0;
#ifdef CFG_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align(sizeof(RTXBD), 8));
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif /* 0 */
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif /* 0 */
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
/* Configure port A pins for Txd and Rxd.
*/
immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
/* Configure port A pins for Txd and Rxd.
*/
immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
/* Configure port B pins for Txd and Rxd.
*/
immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
/* Configure port B pins for Txd and Rxd.
*/
immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
#else
#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
#endif
#if defined(PC_ENET_LBK)
/* Configure port C pins to disable External Loopback
*/
immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
#endif /* PC_ENET_LBK */
/* Configure port C pins to disable External Loopback
*/
immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
#endif /* PC_ENET_LBK */
/* Configure port C pins to enable CLSN and RENA.
*/
immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
/* Configure port C pins to enable CLSN and RENA.
*/
immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
/* Configure port A for TCLK and RCLK.
*/
immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
/* Configure port A for TCLK and RCLK.
*/
immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
/*
* Configure Serial Interface clock routing -- see section 16.7.5.3
* First, clear all SCC bits to zero, then set the ones we want.
*/
/*
* Configure Serial Interface clock routing -- see section 16.7.5.3
* First, clear all SCC bits to zero, then set the ones we want.
*/
immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
/*
* Initialize SDCR -- see section 16.9.23.7
* SDMA configuration register
*/
immr->im_siu_conf.sc_sdcr = 0x01;
/*
* Initialize SDCR -- see section 16.9.23.7
* SDMA configuration register
*/
immr->im_siu_conf.sc_sdcr = 0x01;
/*
* Setup SCC Ethernet Parameter RAM
*/
/*
* Setup SCC Ethernet Parameter RAM
*/
pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++)
{
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
}
for (i = 0; i < PKTBUFSRX; i++) {
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
*/
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++)
{
rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
}
for (i = 0; i < TX_BUF_CNT; i++) {
rtx->txbd[i].cbd_sc =
(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/*
* Enter Command: Initialize Rx Params for SCC
*/
/*
* Enter Command: Initialize Rx Params for SCC
*/
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr =
((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/*
* Ethernet Specific Parameter RAM
* see table 13-16, pg. 660,
* pg. 681 (example with suggested settings)
*/
/*
* Ethernet Specific Parameter RAM
* see table 13-16, pg. 660,
* pg. 681 (example with suggested settings)
*/
pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
#define ea eth_get_dev()->enetaddr
pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
#undef ea
pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
/*
* Enter Command: Initialize Tx Params for SCC
*/
/*
* Enter Command: Initialize Tx Params for SCC
*/
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr =
((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/*
* Mask all Events in SCCM - we use polling mode
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
/*
* Mask all Events in SCCM - we use polling mode
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
/*
* Clear Events in SCCE -- Clear bits by writing 1's
*/
/*
* Clear Events in SCCE -- Clear bits by writing 1's
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
/*
* Initialize GSMR High 32-Bits
* Settings: Normal Mode
*/
/*
* Initialize GSMR High 32-Bits
* Settings: Normal Mode
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
/*
* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
* Settings:
* TCI = Invert
* TPL = 48 bits
* TPP = Repeating 10's
* MODE = Ethernet
*/
/*
* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
* Settings:
* TCI = Invert
* TPL = 48 bits
* TPP = Repeating 10's
* MODE = Ethernet
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \
SCC_GSMRL_TPL_48 | \
SCC_GSMRL_TPP_10 | \
SCC_GSMRL_MODE_ENET);
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
SCC_GSMRL_TPL_48 |
SCC_GSMRL_TPP_10 |
SCC_GSMRL_MODE_ENET);
/*
* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
*/
/*
* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
/*
* Initialize the PSMR
* Settings:
* CRC = 32-Bit CCITT
* NIB = Begin searching for SFD 22 bits after RENA
* FDE = Full Duplex Enable
* LPB = Loopback Enable (Needed when FDE is set)
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 |
/*
* Initialize the PSMR
* Settings:
* CRC = 32-Bit CCITT
* NIB = Begin searching for SFD 22 bits after RENA
* FDE = Full Duplex Enable
* LPB = Loopback Enable (Needed when FDE is set)
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 |
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
SCC_PSMR_FDE |
SCC_PSMR_LPB |
SCC_PSMR_FDE | SCC_PSMR_LPB |
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
SCC_PSMR_BRO |
SCC_PSMR_BRO |
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
SCC_PSMR_PRO |
SCC_PSMR_PRO |
#endif
0;
0;
/*
* Configure Ethernet TENA Signal
*/
/*
* Configure Ethernet TENA Signal
*/
#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
#else
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
/*
* Port C is used to control the PHY,MC68160.
*/
immr->im_ioport.iop_pcdir |=
(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
/*
* Port C is used to control the PHY,MC68160.
*/
immr->im_ioport.iop_pcdir |=
(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */
immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */
#if defined(CONFIG_AMX860)
/*
* Port B is used to control the PHY,MC68160.
*/
immr->im_cpm.cp_pbdir |=
(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
/*
* Port B is used to control the PHY,MC68160.
*/
immr->im_cpm.cp_pbdir |=
(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
#endif /* AMX860 */
immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
#endif /* AMX860 */
#ifdef CONFIG_RPXCLASSIC
*((uchar *)BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *)BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif
#ifdef CONFIG_RPXLITE
*((uchar *)BCSR0) |= BCSR0_ETHEN ;
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
#if defined(CONFIG_QS860T)
/*
* PB27=FDE-, set output low for full duplex
* PB26=Link Test Enable, normally high output
*/
immr->im_cpm.cp_pbdir |= 0x00000030;
immr->im_cpm.cp_pbdat |= 0x00000020;
immr->im_cpm.cp_pbdat &= ~0x00000010;
#endif /* QS860T */
#ifdef CONFIG_MBX
board_ether_init();
board_ether_init ();
#endif
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_ioport.iop_padir |= PA_ENET_PDN;
immr->im_ioport.iop_padat |= PA_ENET_PDN;
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_ioport.iop_padir |= PA_ENET_PDN;
immr->im_ioport.iop_padat |= PA_ENET_PDN;
#elif defined(PB_ENET_PDN)
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
#elif defined(PC_ENET_PDN)
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
#elif defined(PD_ENET_PDN)
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
#endif
#endif
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/*
* Work around transmit problem with first eth packet
*/
/*
* Work around transmit problem with first eth packet
*/
#if defined (CONFIG_FADS)
udelay(10000); /* wait 10 ms */
udelay (10000); /* wait 10 ms */
#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
udelay(100000); /* wait 100 ms */
udelay (100000); /* wait 100 ms */
#endif
return 1;
return 1;
}
static void scc_halt(struct eth_device* dev)
static void scc_halt (struct eth_device *dev)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
volatile immap_t *immr = (immap_t *) CFG_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#if 0
void restart(void)
void restart (void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
volatile immap_t *immr = (immap_t *) CFG_IMMR;
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
#endif
#endif /* CFG_CMD_NET, SCC_ENET */

4
cpu/mpc8xx/serial.c
View File

@ -78,6 +78,10 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
divisor=(50*1000*1000)/16/9600;
}
#ifdef CFG_BRGCLK_PRESCALE
divisor /= CFG_BRGCLK_PRESCALE;
#endif
if(divisor<=0x1000) {
cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
} else {

55
include/commproc.h
View File

@ -1216,6 +1216,60 @@ typedef struct scc_enet {
#endif /* CONFIG_NETVIA */
/*** QS850/QS823 ***************************************************/
#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
#undef FEC_ENET /* Don't use FEC for EThernet */
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
/* SCC2 TXCLK from CLK2
* SCC2 RXCLK from CLK4
* SCC2 Connected to NMSI */
#define SICR_ENET_MASK ((uint)0x00007F00)
#define SICR_ENET_CLKRT ((uint)0x00003D00)
#endif /* CONFIG_QS850/QS823 */
/*** QS860T ***************************************************/
#ifdef CONFIG_QS860T
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for EThernet */
#endif /* CONFIG_FEC_ETHERNET */
/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
#define SICR_ENET_MASK ((uint)0x000000ff)
/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
#define SICR_ENET_CLKRT ((uint)0x0000003D)
#endif /* CONFIG_QS860T */
/*** RPXCLASSIC *****************************************************/
#ifdef CONFIG_RPXCLASSIC
@ -1452,6 +1506,7 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00002e00)
#endif /* CONFIG_V37 */
/*********************************************************************/
/* SCC Event register as used by Ethernet.

571
include/configs/QS823.h Normal file
View File

@ -0,0 +1,571 @@
/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2002
* Simple Network Magic Corporation
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* various debug settings */
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_QS823 1 /* ...on a QS823 module */
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
/* Select the target clock speed */
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
#ifdef CONFIG_CLOCK_16MHZ
#define CONFIG_CLOCK_MULT 512
#endif
#ifdef CONFIG_CLOCK_33MHZ
#define CONFIG_CLOCK_MULT 1024
#endif
#ifdef CONFIG_CLOCK_50MHZ
#define CONFIG_CLOCK_MULT 1525
#endif
#ifdef CONFIG_CLOCK_66MHZ
#define CONFIG_CLOCK_MULT 2048
#endif
#ifdef CONFIG_CLOCK_80MHZ
#define CONFIG_CLOCK_MULT 2441
#endif
/* choose flash size, 4Mb or 8Mb */
#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
/* Define default IP addresses */
#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
/* message to say directly after booting */
#define CONFIG_PREBOOT "echo '';" \
"echo 'type:';" \
"echo 'run boot_nfs to boot to NFS';" \
"echo 'run boot_flash to boot to flash';" \
"echo '';" \
"echo 'run flash_rootfs to install a new rootfs';" \
"echo 'run flash_env to clear the env sector';" \
"echo 'run flash_rw to clear the rw fs';" \
"echo 'run flash_uboot to install a new u-boot';" \
"echo 'run flash_kernel to install a new kernel';"
/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND "run boot_nfs"
#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
/* Our flash filesystem looks like this
*
* 4Mb board:
* ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
* ffec 0000 - ffed ffff read-write filesystem (ext2)
* ffee 0000 - ffef ffff environment
* fff0 0000 - fff1 ffff u-boot
* fff2 0000 - ffff ffff linux kernel
*
* 8Mb board:
* ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
* ffec 0000 - ffed ffff read-write filesystem (ext2)
* ffee 0000 - ffef ffff environment
* fff0 0000 - fff1 ffff u-boot
* fff2 0000 - ffff ffff linux kernel
*
*/
/* environment for 4Mb board */
#ifdef CONFIG_FLASH_4MB
#define CONFIG_EXTRA_ENV_SETTINGS \
"serial#=QS823\0" \
"hostname=qs823\0" \
"netdev=eth0\0" \
"ethaddr=00:01:02:B4:36:56\0" \
"rootpath=/exports/rootfs\0" \
"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
/* fill in variables */ \
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
/* commands */ \
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
/* reinstall flash parts */ \
"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
#endif /* CONFIG_FLASH_4MB */
/* environment for 8Mb board */
#ifdef CONFIG_FLASH_8MB
#define CONFIG_EXTRA_ENV_SETTINGS \
"serial#=QS823\0" \
"hostname=qs823\0" \
"netdev=eth0\0" \
"ethaddr=00:01:02:B4:36:56\0" \
"rootpath=/exports/rootfs\0" \
"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
/* fill in variables */ \
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
/* commands */ \
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
/* reinstall flash parts */ \
"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
#endif /* CONFIG_FLASH_8MB */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_BOOTD | \
CFG_CMD_CONSOLE | \
CFG_CMD_DATE | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
CFG_CMD_IMI | \
CFG_CMD_IMMAP | \
CFG_CMD_MEMORY | \
CFG_CMD_NET | \
CFG_CMD_RUN)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
#define CFG_ENV_SIZE 0x2000 /* 8kb */
#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* TODO flash parameters
* FLASH organization for Intel Strataflash
*/
#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
*/
/* MF (Multiplication Factor of SPLL) */
/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
*/
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
#define CFG_BRGCLK_PRESCALE 1
#endif
#if defined(CONFIG_CLOCK_66MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE 4
#endif
#if defined(CONFIG_CLOCK_80MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE 4
#endif
#define SCCR_MASK CFG_SCCR
/*-----------------------------------------------------------------------
* Debug Enable Register
* 0x73E67C0F - All interrupts handled by BDM
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
*-----------------------------------------------------------------------
#define CFG_DER 0x73E67C0F
#define CFG_DER 0x0082400F
#-------------------------------------------------------------------------
# Program the Debug Enable Register (DER). This register provides the user
# with the reason for entering into the debug mode. We want all conditions
# to end up as an exception. We don't want to enter into debug mode for
# any condition. See the back of of the Development Support section of the
# MPC860 User Manual for a description of this register.
#-------------------------------------------------------------------------
*/
#define CFG_DER 0
/*-----------------------------------------------------------------------
* Memory Controller Initialization Constants
*-----------------------------------------------------------------------
*/
/*
* BR0 and OR0 (AMD dual FLASH devices)
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
*/
#define CFG_PRELIM_OR_AM
#define CFG_OR_TIMING_FLASH
/*
*-----------------------------------------------------------------------
* Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
* flash that resides on the QS823.
*-----------------------------------------------------------------------
*/
/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
/* represents a minumum 32K block size. */
#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
#define CFG_BR0_PRELIM (vBR0_BA | BR_V)
/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
/* which defines a 8 Mbyte memory block. */
#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
/* 0101 = Add a 5 clock cycle wait state */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
#endif
#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
/* 0011 = Add a 3 clock cycle wait state */
/* 29.8ns clock * (3 + 2) = 149ns cycle time */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
#endif
#if defined(CONFIG_CLOCK_16MHZ)
/* 0010 = Add a 2 clock cycle wait state */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
#endif
/*
* BR1 and OR1 (SDRAM)
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
* Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
*/
#define SDRAM_BASE 0x00000000 /* SDRAM bank */
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
* represents a 128 Mbyte block the DRAM in
* this address base.
*/
#define vOR1_AM ((0xF800 << 16) + (0 << 15))
#define vBR1_BA ((0x0000 << 16) + (0 << 15))
#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
/* Machine A Mode Register */
/* PTA Periodic Timer A */
#if defined(CONFIG_CLOCK_80MHZ)
#define vMAMR_PTA (19 << 24)
#endif
#if defined(CONFIG_CLOCK_66MHZ)
#define vMAMR_PTA (16 << 24)
#endif
#if defined(CONFIG_CLOCK_50MHZ)
#define vMAMR_PTA (195 << 24)
#endif
#if defined(CONFIG_CLOCK_33MHZ)
#define vMAMR_PTA (131 << 24)
#endif
#if defined(CONFIG_CLOCK_16MHZ)
#define vMAMR_PTA (65 << 24)
#endif
/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* For boards with 32M of SDRAM */
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* Memory Periodic Timer Prescaler Register */
#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
/* Divide by 32 */
#define CFG_MPTPR 0x02
#endif
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
/* Divide by 16 */
#define CFG_MPTPR 0x04
#endif
/*
* BR2 and OR2 (Unused)
* Base address = 0xF020_0000 - 0xF020_0FFF
*
*/
#define CFG_OR2_PRELIM 0xFFF00000
#define CFG_BR2_PRELIM 0xF0200000
/*
* BR3 and OR3 (External Bus CS3)
* Base address = 0xF030_0000 - 0xF030_0FFF
*
*/
#define CFG_OR3_PRELIM 0xFFF00000
#define CFG_BR3_PRELIM 0xF0300000
/*
* BR4 and OR4 (External Bus CS3)
* Base address = 0xF040_0000 - 0xF040_0FFF
*
*/
#define CFG_OR4_PRELIM 0xFFF00000
#define CFG_BR4_PRELIM 0xF0400000
/*
* BR4 and OR4 (External Bus CS3)
* Base address = 0xF050_0000 - 0xF050_0FFF
*
*/
#define CFG_OR5_PRELIM 0xFFF00000
#define CFG_BR5_PRELIM 0xF0500000
/*
* BR6 and OR6 (Unused)
* Base address = 0xF060_0000 - 0xF060_0FFF
*
*/
#define CFG_OR6_PRELIM 0xFFF00000
#define CFG_BR6_PRELIM 0xF0600000
/*
* BR7 and OR7 (Unused)
* Base address = 0xF070_0000 - 0xF070_0FFF
*
*/
#define CFG_OR7_PRELIM 0xFFF00000
#define CFG_BR7_PRELIM 0xF0700000
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
#endif /* __CONFIG_H */

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include/configs/QS850.h Normal file
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/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2002
* Simple Network Magic Corporation
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* various debug settings */
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_QS850 1 /* ...on a QS850 module */
#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
/* Select the target clock speed */
#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
#ifdef CONFIG_CLOCK_16MHZ
#define CONFIG_CLOCK_MULT 512
#endif
#ifdef CONFIG_CLOCK_33MHZ
#define CONFIG_CLOCK_MULT 1024
#endif
#ifdef CONFIG_CLOCK_50MHZ
#define CONFIG_CLOCK_MULT 1525
#endif
#ifdef CONFIG_CLOCK_66MHZ
#define CONFIG_CLOCK_MULT 2048
#endif
#ifdef CONFIG_CLOCK_80MHZ
#define CONFIG_CLOCK_MULT 2441
#endif
/* choose flash size, 4Mb or 8Mb */
#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
/* Define default IP addresses */
#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
/* message to say directly after booting */
#define CONFIG_PREBOOT "echo '';" \
"echo 'type:';" \
"echo 'run boot_nfs to boot to NFS';" \
"echo 'run boot_flash to boot to flash';" \
"echo '';" \
"echo 'run flash_rootfs to install a new rootfs';" \
"echo 'run flash_env to clear the env sector';" \
"echo 'run flash_rw to clear the rw fs';" \
"echo 'run flash_uboot to install a new u-boot';" \
"echo 'run flash_kernel to install a new kernel';"
/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND "run boot_nfs"
#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
/* Our flash filesystem looks like this
*
* 4Mb board:
* ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
* ffec 0000 - ffed ffff read-write filesystem (ext2)
* ffee 0000 - ffef ffff environment
* fff0 0000 - fff1 ffff u-boot
* fff2 0000 - ffff ffff linux kernel
*
* 8Mb board:
* ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
* ffec 0000 - ffed ffff read-write filesystem (ext2)
* ffee 0000 - ffef ffff environment
* fff0 0000 - fff1 ffff u-boot
* fff2 0000 - ffff ffff linux kernel
*
*/
/* environment for 4Mb board */
#ifdef CONFIG_FLASH_4MB
#define CONFIG_EXTRA_ENV_SETTINGS \
"serial#=QS850\0" \
"hostname=qs850\0" \
"netdev=eth0\0" \
"ethaddr=00:01:02:B4:36:56\0" \
"rootpath=/exports/rootfs\0" \
"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
/* fill in variables */ \
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
/* commands */ \
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
/* reinstall flash parts */ \
"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
#endif /* CONFIG_FLASH_4MB */
/* environment for 8Mb board */
#ifdef CONFIG_FLASH_8MB
#define CONFIG_EXTRA_ENV_SETTINGS \
"serial#=QS850\0" \
"hostname=qs850\0" \
"netdev=eth0\0" \
"ethaddr=00:01:02:B4:36:56\0" \
"rootpath=/exports/rootfs\0" \
"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
/* fill in variables */ \
"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
/* commands */ \
"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
/* reinstall flash parts */ \
"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
#endif /* CONFIG_FLASH_8MB */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_BOOTD | \
CFG_CMD_CONSOLE | \
CFG_CMD_DATE | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
CFG_CMD_IMI | \
CFG_CMD_IMMAP | \
CFG_CMD_MEMORY | \
CFG_CMD_NET | \
CFG_CMD_RUN)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Environment variable storage is in FLASH, one sector before U-boot
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
#define CFG_ENV_SIZE 0x2000 /* 8kb */
#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* TODO flash parameters
* FLASH organization for Intel Strataflash
*/
#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
*/
/* MF (Multiplication Factor of SPLL) */
/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
*/
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
#define CFG_BRGCLK_PRESCALE 1
#endif
#if defined(CONFIG_CLOCK_66MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE 4
#endif
#if defined(CONFIG_CLOCK_80MHZ)
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE 4
#endif
#define SCCR_MASK CFG_SCCR
/*-----------------------------------------------------------------------
* Debug Enable Register
* 0x73E67C0F - All interrupts handled by BDM
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
*-----------------------------------------------------------------------
#define CFG_DER 0x73E67C0F
#define CFG_DER 0x0082400F
#-------------------------------------------------------------------------
# Program the Debug Enable Register (DER). This register provides the user
# with the reason for entering into the debug mode. We want all conditions
# to end up as an exception. We don't want to enter into debug mode for
# any condition. See the back of of the Development Support section of the
# MPC860 User Manual for a description of this register.
#-------------------------------------------------------------------------
*/
#define CFG_DER 0
/*-----------------------------------------------------------------------
* Memory Controller Initialization Constants
*-----------------------------------------------------------------------
*/
/*
* BR0 and OR0 (AMD dual FLASH devices)
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
*/
#define CFG_PRELIM_OR_AM
#define CFG_OR_TIMING_FLASH
/*
*-----------------------------------------------------------------------
* Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
* flash that resides on the QS850.
*-----------------------------------------------------------------------
*/
/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
/* represents a minumum 32K block size. */
#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
#define CFG_BR0_PRELIM (vBR0_BA | BR_V)
/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
/* which defines a 8 Mbyte memory block. */
#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
/* 0101 = Add a 5 clock cycle wait state */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
#endif
#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
/* 0011 = Add a 3 clock cycle wait state */
/* 29.8ns clock * (3 + 2) = 149ns cycle time */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
#endif
#if defined(CONFIG_CLOCK_16MHZ)
/* 0010 = Add a 2 clock cycle wait state */
#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
#endif
/*
* BR1 and OR1 (SDRAM)
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
* Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
*/
#define SDRAM_BASE 0x00000000 /* SDRAM bank */
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
* represents a 128 Mbyte block the DRAM in
* this address base.
*/
#define vOR1_AM ((0xF800 << 16) + (0 << 15))
#define vBR1_BA ((0x0000 << 16) + (0 << 15))
#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
/* Machine A Mode Register */
/* PTA Periodic Timer A */
#if defined(CONFIG_CLOCK_80MHZ)
#define vMAMR_PTA (19 << 24)
#endif
#if defined(CONFIG_CLOCK_66MHZ)
#define vMAMR_PTA (16 << 24)
#endif
#if defined(CONFIG_CLOCK_50MHZ)
#define vMAMR_PTA (195 << 24)
#endif
#if defined(CONFIG_CLOCK_33MHZ)
#define vMAMR_PTA (131 << 24)
#endif
#if defined(CONFIG_CLOCK_16MHZ)
#define vMAMR_PTA (65 << 24)
#endif
/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* For boards with 32M of SDRAM */
#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* Memory Periodic Timer Prescaler Register */
#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
/* Divide by 32 */
#define CFG_MPTPR 0x02
#endif
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
/* Divide by 16 */
#define CFG_MPTPR 0x04
#endif
/*
* BR2 and OR2 (Unused)
* Base address = 0xF020_0000 - 0xF020_0FFF
*
*/
#define CFG_OR2_PRELIM 0xFFF00000
#define CFG_BR2_PRELIM 0xF0200000
/*
* BR3 and OR3 (External Bus CS3)
* Base address = 0xF030_0000 - 0xF030_0FFF
*
*/
#define CFG_OR3_PRELIM 0xFFF00000
#define CFG_BR3_PRELIM 0xF0300000
/*
* BR4 and OR4 (External Bus CS3)
* Base address = 0xF040_0000 - 0xF040_0FFF
*
*/
#define CFG_OR4_PRELIM 0xFFF00000
#define CFG_BR4_PRELIM 0xF0400000
/*
* BR4 and OR4 (External Bus CS3)
* Base address = 0xF050_0000 - 0xF050_0FFF
*
*/
#define CFG_OR5_PRELIM 0xFFF00000
#define CFG_BR5_PRELIM 0xF0500000
/*
* BR6 and OR6 (Unused)
* Base address = 0xF060_0000 - 0xF060_0FFF
*
*/
#define CFG_OR6_PRELIM 0xFFF00000
#define CFG_BR6_PRELIM 0xF0600000
/*
* BR7 and OR7 (Unused)
* Base address = 0xF070_0000 - 0xF070_0FFF
*
*/
#define CFG_OR7_PRELIM 0xFFF00000
#define CFG_BR7_PRELIM 0xF0700000
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
#endif /* __CONFIG_H */

413
include/configs/QS860T.h Normal file
View File

@ -0,0 +1,413 @@
/*
* (C) Copyright 2003
* MuLogic B.V.
*
* (C) Copyright 2002
* Simple Network Magic Corporation
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* various debug settings */
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */
#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_QS860T 1 /* ...on a QS860T module */
#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
#define FEC_INTERRUPT SIU_LEVEL1
#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
#define CFG_DISCOVER_PHY
#undef CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/* Pass clocks to Linux 2.4.18 in Hz */
#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
#define CONFIG_PREBOOT "echo;" \
"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
"echo"
#undef CONFIG_BOOTARGS
/* TODO compare against CADM860 */
#define CONFIG_BOOTCOMMAND "bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_STATUS_LED /* Status LED disabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_REGINFO | \
CFG_CMD_IMMAP | \
CFG_CMD_ASKENV | \
CFG_CMD_NET | \
CFG_CMD_DHCP | \
CFG_CMD_DATE )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/* TODO */
#if 0
/* Look at these */
CONFIG_IPADDR
CONFIG_SERVERIP
CONFIG_I2C
CONFIG_SPI
#endif
/*
* Environment variable storage is in NVRAM
*/
#define CFG_ENV_IS_IN_NVRAM 1
#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */
#define CFG_ENV_ADDR 0xD100E000
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* TODO - size? */
#define CFG_MEMTEST_START 0x0400000 /* memtest works */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFFF00000
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/* TODO flash parameters */
/*-----------------------------------------------------------------------
* FLASH organization for Intel Strataflash
*/
#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#undef CFG_ENV_IS_IN_FLASH
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
#else
#define CFG_SYPCR 0xFFFFFF88
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
*/
#define CFG_SIUMCR 0x00620000
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
*/
#define CFG_TBSCR 0x00C3
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
*/
#define CFG_PISCR 0x0082
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
*/
#define CFG_PLPRCR 0x0090D000
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR 0x02000000
/*-----------------------------------------------------------------------
* Debug Enable Register
* 0x73E67C0F - All interrupts handled by BDM
* 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
*-----------------------------------------------------------------------
#define CFG_DER 0x73E67C0F
*/
#define CFG_DER 0x0082400F
/*-----------------------------------------------------------------------
* Memory Controller Initialization Constants
*-----------------------------------------------------------------------
*/
/*
* BR0 and OR0 (AMD 512K Socketed FLASH)
* Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
*/
#define CFG_PRELIM_OR_AM
#define CFG_OR_TIMING_FLASH
#define FLASH_BASE0_PRELIM 0xFFF00001
#define CFG_OR0_PRELIM 0xFFF80D42
#define CFG_BR0_PRELIM 0xFFF00401
/*
* BR1 and OR1 (Intel 8M StrataFLASH)
* Base address = 0xD000_0000 - 0xD07F_FFFF
*/
#define FLASH_BASE1_PRELIM 0xD0000000
#define CFG_OR1_PRELIM 0xFF800D42
#define CFG_BR1_PRELIM 0xD0000801
/* #define CFG_OR1 0xFF800D42 */
/* #define CFG_BR1 0xD0000801 */
/*
* BR2 and OR2 (SDRAM)
* Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
* Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
* Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
*
*/
#define SDRAM_BASE 0x00000000 /* SDRAM bank */
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
/* SDRAM timing */
#define SDRAM_TIMING 0x00000A00
/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */
/* For boards with 64M of SDRAM */
#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */
/* TODO - determine real value */
#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */
#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
#define CFG_BR2 (SDRAM_BASE | 0x000000C1)
/*
* BR3 and OR3 (NVRAM, Sipex, NAND Flash)
* Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
* Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
* Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
* Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
*
*/
#define CFG_OR3_PRELIM 0xFFC00DF6
#define CFG_BR3_PRELIM 0xD1000401
/* #define CFG_OR3 0xFFC00DF6 */
/* #define CFG_BR3 0xD1000401 */
/*
* BR4 and OR4 (Unused)
* Base address = 0xE000_0000 - 0xE3FF_FFFF
*
*/
#define CFG_OR4_PRELIM 0xFF000000
#define CFG_BR4_PRELIM 0xE0000000
/* #define CFG_OR4 0xFF000000 */
/* #define CFG_BR4 0xE0000000 */
/*
* BR5 and OR5 (Expansion bus)
* Base address = 0xE400_0000 - 0xE7FF_FFFF
*
*/
#define CFG_OR5_PRELIM 0xFF000000
#define CFG_BR5_PRELIM 0xE4000000
/* #define CFG_OR5 0xFF000000 */
/* #define CFG_BR5 0xE4000000 */
/*
* BR6 and OR6 (Expansion bus)
* Base address = 0xE800_0000 - 0xEBFF_FFFF
*
*/
#define CFG_OR6_PRELIM 0xFF000000
#define CFG_BR6_PRELIM 0xE8000000
/* #define CFG_OR6 0xFF000000 */
/* #define CFG_BR6 0xE8000000 */
/*
* BR7 and OR7 (Expansion bus)
* Base address = 0xEC00_0000 - 0xEFFF_FFFF
*
*/
#define CFG_OR7_PRELIM 0xFF000000
#define CFG_BR7_PRELIM 0xE8000000
/* #define CFG_OR7 0xFF000000 */
/* #define CFG_BR7 0xE8000000 */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Sanity checks
*/
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif
#endif /* __CONFIG_H */

5
include/flash.h
View File

@ -148,6 +148,9 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
@ -322,6 +325,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
#define FLASH_28F256L18T 0x00A8
#define FLASH_AMDL163T 0x00A2 /* AMD AM29DL163T (2M x 16 ) */
#define FLASH_AMDL163B 0x00A3
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */