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mx25: Fix decode_pll

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The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau 2012-09-27 10:26:54 +00:00 committed by Tom Rini
parent 323846561a
commit 3c76add262
1 changed files with 6 additions and 3 deletions
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9
arch/arm/cpu/arm926ejs/mx25/generic.c
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@ -48,7 +48,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{ {
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT) unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK; & CCM_PLL_MFI_MASK;
unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT) int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK; & CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT) unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK; & CCM_PLL_MFD_MASK;
@ -56,9 +56,12 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
& CCM_PLL_PD_MASK; & CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi; mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn), return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
(mfd + 1) * (pd + 1)); mfd * pd);
} }
static ulong imx_get_mpllclk(void) static ulong imx_get_mpllclk(void)