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Coding Style cleanup, update CHANGELOG

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-11-02 16:14:22 +01:00
parent 3ec53148eb
commit 3cbd823116
21 changed files with 2599 additions and 241 deletions
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2368
CHANGELOG
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File diff suppressed because it is too large Load Diff

2
board/amcc/canyonlands/init.S
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@ -98,7 +98,7 @@ tlbtab:
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
#if defined(CONFIG_RAPIDIO) #if defined(CONFIG_RAPIDIO)
/* TLB-entries for RapidIO (SRIO) */ /* TLB-entries for RapidIO (SRIO) */
tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR, tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
0xD, AC_R|AC_W|SA_G|SA_I) 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR, tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,

2
board/atum8548/atum8548.c
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@ -377,7 +377,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

6
board/freescale/mpc8536ds/mpc8536ds.c
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@ -439,8 +439,8 @@ int board_early_init_r(void)
*/ */
/* Flush d-cache and invalidate i-cache of any FLASH data */ /* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache(); flush_dcache();
invalidate_icache(); invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */ /* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel); disable_tlb(flash_esel);
@ -646,7 +646,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

2
board/freescale/mpc8544ds/mpc8544ds.c
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@ -488,7 +488,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

2
board/freescale/mpc8548cds/mpc8548cds.c
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@ -479,7 +479,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_pci_setup(void *blob, bd_t *bd) void ft_pci_setup(void *blob, bd_t *bd)
{ {

2
board/freescale/mpc8568mds/mpc8568mds.c
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@ -496,7 +496,7 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

6
board/freescale/mpc8572ds/mpc8572ds.c
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@ -362,8 +362,8 @@ int board_early_init_r(void)
*/ */
/* Flush d-cache and invalidate i-cache of any FLASH data */ /* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache(); flush_dcache();
invalidate_icache(); invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */ /* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel); disable_tlb(flash_esel);
@ -560,7 +560,7 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

2
board/freescale/mpc8610hpcd/mpc8610hpcd.c
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@ -403,7 +403,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void void
ft_board_setup(void *blob, bd_t *bd) ft_board_setup(void *blob, bd_t *bd)

16
board/freescale/mpc8641hpcn/ddr.c
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@ -47,12 +47,12 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
} }
typedef struct { typedef struct {
u32 datarate_mhz_low; u32 datarate_mhz_low;
u32 datarate_mhz_high; u32 datarate_mhz_high;
u32 n_ranks; u32 n_ranks;
u32 clk_adjust; u32 clk_adjust;
u32 cpo; u32 cpo;
u32 write_data_delay; u32 write_data_delay;
} board_specific_parameters_t; } board_specific_parameters_t;
/* XXX: these values need to be checked for all interleaving modes. */ /* XXX: these values need to be checked for all interleaving modes. */
@ -84,7 +84,7 @@ const board_specific_parameters_t board_specific_parameters[2][16] = {
{ {
/* memory controller 1 */ /* memory controller 1 */
/* lo| hi| num| clk| cpo|wrdata */ /* lo| hi| num| clk| cpo|wrdata */
/* mhz| mhz|ranks|adjst| | delay */ /* mhz| mhz|ranks|adjst| | delay */
{ 0, 333, 4, 7, 7, 3}, { 0, 333, 4, 7, 7, 3},
{334, 400, 4, 7, 9, 3}, {334, 400, 4, 7, 9, 3},
@ -129,7 +129,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
if (i&1) { /* odd CS */ if (i&1) { /* odd CS */
popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 0;
} else { /* even CS */ } else { /* even CS */
if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) && if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) &&
(pdimm[i/2].n_ranks != 0)) { (pdimm[i/2].n_ranks != 0)) {
popts->cs_local_opts[i].odt_rd_cfg = 3; popts->cs_local_opts[i].odt_rd_cfg = 3;

2
board/freescale/mpc8641hpcn/mpc8641hpcn.c
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@ -270,7 +270,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void void
ft_board_setup(void *blob, bd_t *bd) ft_board_setup(void *blob, bd_t *bd)

276
board/keymile/mgcoge/mgcoge.c
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@ -45,152 +45,152 @@ extern int ivm_read_eeprom (void);
const iop_conf_t iop_conf_tab[4][32] = { const iop_conf_t iop_conf_tab[4][32] = {
/* Port A */ /* Port A */
{ /* conf ppar psor pdir podr pdat */ { /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
/* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
/* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */ /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
/* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */ /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
/* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */ /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
/* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */ /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
/* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */ /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
/* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */ /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
/* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */ /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
/* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */ /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
/* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */ /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
/* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */ /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
/* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */ /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
/* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */ /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
}, },
/* Port B */ /* Port B */
{ /* conf ppar psor pdir podr pdat */ { /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
/* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
/* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
/* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */ /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
/* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
/* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
/* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
/* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
/* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
/* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
/* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
/* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
/* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
/* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
}, },
/* Port C */ /* Port C */
{ /* conf ppar psor pdir podr pdat */ { /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
/* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */ /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */
/* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */ /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
/* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */ /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */
/* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */ /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
}, },
/* Port D */ /* Port D */
{ /* conf ppar psor pdir podr pdat */ { /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
/* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
/* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
/* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */ /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
#if defined(CONFIG_HARD_I2C) #if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else #else
/* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */ /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
#endif #endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
} }
}; };
@ -309,10 +309,10 @@ int hush_init_var (void)
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
extern int fdt_set_node_and_value (void *blob, extern int fdt_set_node_and_value (void *blob,
char *nodename, char *nodename,
char *regname, char *regname,
void *var, void *var,
int size); int size);
/* /*
* update "memory" property in the blob * update "memory" property in the blob

8
board/keymile/mgsuvd/mgsuvd.c
View File

@ -151,10 +151,10 @@ int hush_init_var (void)
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
extern int fdt_set_node_and_value (void *blob, extern int fdt_set_node_and_value (void *blob,
char *nodename, char *nodename,
char *regname, char *regname,
void *var, void *var,
int size); int size);
/* /*
* update "memory" property in the blob * update "memory" property in the blob

2
board/sbc8548/sbc8548.c
View File

@ -530,7 +530,7 @@ int last_stage_init(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup(void *blob, bd_t *bd) void ft_board_setup(void *blob, bd_t *bd)
{ {

2
board/sbc8641d/sbc8641d.c
View File

@ -322,7 +322,7 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP) #if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup (void *blob, bd_t *bd) void ft_board_setup (void *blob, bd_t *bd)
{ {

4
board/tqc/tqm85xx/tqm85xx.c
View File

@ -23,7 +23,7 @@
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
@ -702,7 +702,7 @@ void pci_init_board (void)
#ifdef CONFIG_OF_BOARD_SETUP #ifdef CONFIG_OF_BOARD_SETUP
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose); struct pci_controller *hose);
void ft_board_setup (void *blob, bd_t *bd) void ft_board_setup (void *blob, bd_t *bd)
{ {

6
common/cmd_i2c.c
View File

@ -249,7 +249,6 @@ int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return mod_i2c_mem (cmdtp, 1, flag, argc, argv); return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
} }
int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
return mod_i2c_mem (cmdtp, 0, flag, argc, argv); return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
@ -339,7 +338,6 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0); return (0);
} }
/* Calculate a CRC on memory /* Calculate a CRC on memory
* *
* Syntax: * Syntax:
@ -409,7 +407,6 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0; return 0;
} }
/* Modify memory. /* Modify memory.
* *
* Syntax: * Syntax:
@ -587,7 +584,6 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0; return 0;
} }
/* /*
* Syntax: * Syntax:
* iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
@ -658,7 +654,6 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0; return 0;
} }
/* /*
* The SDRAM command is separately configured because many * The SDRAM command is separately configured because many
* (most?) embedded boards don't use SDRAM DIMMs. * (most?) embedded boards don't use SDRAM DIMMs.
@ -1601,4 +1596,3 @@ int i2x_mux_select_mux(int bus)
return 0; return 0;
} }
#endif /* CONFIG_I2C_MUX */ #endif /* CONFIG_I2C_MUX */

54
disk/part_efi.h
View File

@ -43,33 +43,33 @@
#define GPT_ENTRY_NAME "gpt" #define GPT_ENTRY_NAME "gpt"
#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \ #define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \
((efi_guid_t) \ ((efi_guid_t) \
{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
(b) & 0xff, ((b) >> 8) & 0xff, \ (b) & 0xff, ((b) >> 8) & 0xff, \
(c) & 0xff, ((c) >> 8) & 0xff, \ (c) & 0xff, ((c) >> 8) & 0xff, \
(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
#define PARTITION_SYSTEM_GUID \ #define PARTITION_SYSTEM_GUID \
EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \ EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B) 0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
#define LEGACY_MBR_PARTITION_GUID \ #define LEGACY_MBR_PARTITION_GUID \
EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \ EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F) 0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
#define PARTITION_MSFT_RESERVED_GUID \ #define PARTITION_MSFT_RESERVED_GUID \
EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \ EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE) 0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
#define PARTITION_BASIC_DATA_GUID \ #define PARTITION_BASIC_DATA_GUID \
EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \ EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7) 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
#define PARTITION_LINUX_RAID_GUID \ #define PARTITION_LINUX_RAID_GUID \
EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \ EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e) 0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
#define PARTITION_LINUX_SWAP_GUID \ #define PARTITION_LINUX_SWAP_GUID \
EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \ EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f) 0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
#define PARTITION_LINUX_LVM_GUID \ #define PARTITION_LINUX_LVM_GUID \
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
/* linux/include/efi.h */ /* linux/include/efi.h */
typedef unsigned short efi_char16_t; typedef unsigned short efi_char16_t;
@ -80,14 +80,14 @@ typedef struct {
/* based on linux/include/genhd.h */ /* based on linux/include/genhd.h */
struct partition { struct partition {
unsigned char boot_ind; /* 0x80 - active */ unsigned char boot_ind; /* 0x80 - active */
unsigned char head; /* starting head */ unsigned char head; /* starting head */
unsigned char sector; /* starting sector */ unsigned char sector; /* starting sector */
unsigned char cyl; /* starting cylinder */ unsigned char cyl; /* starting cylinder */
unsigned char sys_ind; /* What partition type */ unsigned char sys_ind; /* What partition type */
unsigned char end_head; /* end head */ unsigned char end_head; /* end head */
unsigned char end_sector; /* end sector */ unsigned char end_sector; /* end sector */
unsigned char end_cyl; /* end cylinder */ unsigned char end_cyl; /* end cylinder */
unsigned char start_sect[4]; /* starting sector counting from 0 */ unsigned char start_sect[4]; /* starting sector counting from 0 */
unsigned char nr_sects[4]; /* nr of sectors in partition */ unsigned char nr_sects[4]; /* nr of sectors in partition */
} __attribute__ ((packed)); } __attribute__ ((packed));
@ -135,4 +135,4 @@ typedef struct _legacy_mbr {
unsigned char signature[2]; unsigned char signature[2];
} __attribute__ ((packed)) legacy_mbr; } __attribute__ ((packed)) legacy_mbr;
#endif /* _DISK_PART_EFI_H */ #endif /* _DISK_PART_EFI_H */

63
include/configs/MPC8572DS.h
View File

@ -158,7 +158,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Localbus non-cacheable * Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
@ -268,50 +268,49 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0x80000,\
CONFIG_SYS_NAND_BASE + 0xC0000} CONFIG_SYS_NAND_BASE + 0xC0000}
#define CONFIG_SYS_MAX_NAND_DEVICE 4 #define CONFIG_SYS_MAX_NAND_DEVICE 4
#define NAND_MAX_CHIPS 1 #define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */ /* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \ | OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \ | OR_FCM_CSCT \
| OR_FCM_CST \ | OR_FCM_CST \
| OR_FCM_CHT \ | OR_FCM_CHT \
| OR_FCM_SCY_1 \ | OR_FCM_SCY_1 \
| OR_FCM_TRLX \ | OR_FCM_TRLX \
| OR_FCM_EHTR) | OR_FCM_EHTR)
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/* Serial Port - controlled on board with jumper J8 /* Serial Port - controlled on board with jumper J8

13
include/configs/fx12mm.h
View File

@ -25,11 +25,10 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
/* /*
Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec, * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
see http://www.em.avnet.com * see http://www.em.avnet.com
*/ */
#ifndef __CONFIG_FX12_H #ifndef __CONFIG_FX12_H
#define __CONFIG_FX12_H #define __CONFIG_FX12_H
@ -54,7 +53,7 @@
/*Misc*/ /*Misc*/
#define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" #define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/ /*Flash*/
#define CONFIG_SYS_FLASH_SIZE (4*1024*1024) #define CONFIG_SYS_FLASH_SIZE (4*1024*1024)
@ -62,8 +61,6 @@
#define MTDIDS_DEFAULT "nor0=fx12mm-flash" #define MTDIDS_DEFAULT "nor0=fx12mm-flash"
#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)" #define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)"
#include "configs/xilinx-ppc405.h" #include "configs/xilinx-ppc405.h"
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

2
lib_ppc/bootm.c
View File

@ -173,7 +173,7 @@ static void boot_prep_linux(void)
#if (CONFIG_NUM_CPUS > 1) #if (CONFIG_NUM_CPUS > 1)
/* if we are MP make sure to flush the dcache() to any changes are made /* if we are MP make sure to flush the dcache() to any changes are made
* visibile to all other cores */ * visibile to all other cores */
flush_dcache(); flush_dcache();
#endif #endif
return ; return ;
} }