mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-11-04 03:04:52 -05:00
Merge with /home/wd/git/u-boot/master
This commit is contained in:
Wolfgang Denk
commit
46044b4817
2
Makefile
2
Makefile
@ -1737,7 +1737,7 @@ clean:
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rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend
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rm -f tools/env/fw_printenv tools/env/fw_setenv
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rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
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rm -f board/trab/trab_fkt
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rm -f board/trab/trab_fkt board/voiceblue/eeprom
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clobber: clean
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find . -type f \( -name .depend \
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@ -38,72 +38,79 @@
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* Utility to send the preamble, address, and register (common to read
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* and write).
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*/
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static void miiphy_pre(char read,
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unsigned char addr,
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unsigned char reg)
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static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
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{
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int j; /* counter */
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volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
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int j; /* counter */
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#ifndef CONFIG_EP8248
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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MDIO_ACTIVE;
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MDIO(1);
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for(j = 0; j < 32; j++)
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{
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MDC(0);
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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}
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MDIO_ACTIVE;
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MDIO (1);
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for (j = 0; j < 32; j++) {
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
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MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
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MDC(0); MDIO(read); MIIDELAY; MDC(1); MIIDELAY;
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MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY;
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/* send the start bit (01) and the read opcode (10) or write (10) */
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MDC (0);
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MDIO (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (1);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (read);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (!read);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* send the PHY address */
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for(j = 0; j < 5; j++)
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{
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MDC(0);
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if((addr & 0x10) == 0)
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{
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MDIO(0);
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}
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else
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{
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MDIO(1);
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}
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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addr <<= 1;
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}
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/* send the PHY address */
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for (j = 0; j < 5; j++) {
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MDC (0);
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if ((addr & 0x10) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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addr <<= 1;
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}
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/* send the register address */
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for(j = 0; j < 5; j++)
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{
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MDC(0);
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if((reg & 0x10) == 0)
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{
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MDIO(0);
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}
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else
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{
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MDIO(1);
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}
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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reg <<= 1;
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}
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/* send the register address */
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for (j = 0; j < 5; j++) {
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MDC (0);
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if ((reg & 0x10) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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reg <<= 1;
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}
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}
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@ -114,66 +121,63 @@ static void miiphy_pre(char read,
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* Returns:
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* 0 on success
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*/
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int miiphy_read(unsigned char addr,
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unsigned char reg,
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unsigned short *value)
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int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
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{
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short rdreg; /* register working value */
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int j; /* counter */
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volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
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miiphy_pre(1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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MDC(0);
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MDIO_TRISTATE;
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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/* check the turnaround bit: the PHY should be driving it to zero */
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if(MDIO_READ != 0)
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{
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/* puts ("PHY didn't drive TA low\n"); */
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for(j = 0; j < 32; j++)
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{
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MDC(0);
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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}
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return(-1);
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}
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MDC(0);
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MIIDELAY;
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for(j = 0; j < 16; j++)
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{
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MDC(1);
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MIIDELAY;
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rdreg <<= 1;
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rdreg |= MDIO_READ;
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MDC(0);
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MIIDELAY;
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}
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MDC(1);
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MIIDELAY;
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MDC(0);
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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*value = rdreg;
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#ifdef DEBUG
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printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
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short rdreg; /* register working value */
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int j; /* counter */
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#ifndef CONFIG_EP8248
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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return 0;
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miiphy_pre (1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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MDC (0);
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MDIO_TRISTATE;
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* check the turnaround bit: the PHY should be driving it to zero */
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if (MDIO_READ != 0) {
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/* puts ("PHY didn't drive TA low\n"); */
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for (j = 0; j < 32; j++) {
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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}
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return (-1);
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}
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MDC (0);
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MIIDELAY;
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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MDC (1);
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MIIDELAY;
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rdreg <<= 1;
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rdreg |= MDIO_READ;
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MDC (0);
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MIIDELAY;
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}
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MDC (1);
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MIIDELAY;
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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*value = rdreg;
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#ifdef DEBUG
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printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
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#endif
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return 0;
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}
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@ -184,47 +188,51 @@ int miiphy_read(unsigned char addr,
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* Returns:
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* 0 on success
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*/
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int miiphy_write(unsigned char addr,
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unsigned char reg,
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unsigned short value)
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int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
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{
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int j; /* counter */
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volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT);
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int j; /* counter */
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#ifndef CONFIG_EP8248
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volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
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#endif
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miiphy_pre(0, addr, reg);
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miiphy_pre (0, addr, reg);
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/* send the turnaround (10) */
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MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY;
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MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY;
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/* send the turnaround (10) */
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MDC (0);
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MDIO (1);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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MDC (0);
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MDIO (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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/* write 16 bits of register data, MSB first */
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for(j = 0; j < 16; j++)
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{
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MDC(0);
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if((value & 0x00008000) == 0)
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{
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MDIO(0);
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}
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else
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{
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MDIO(1);
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}
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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value <<= 1;
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}
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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MDC (0);
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if ((value & 0x00008000) == 0) {
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MDIO (0);
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} else {
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MDIO (1);
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}
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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MDIO_TRISTATE;
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MDC(0);
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MIIDELAY;
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MDC(1);
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MIIDELAY;
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/*
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* Tri-state the MDIO line.
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*/
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MDIO_TRISTATE;
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MDC (0);
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MIIDELAY;
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MDC (1);
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MIIDELAY;
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return 0;
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return 0;
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}
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#endif /* CONFIG_BITBANGMII */
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@ -128,7 +128,7 @@
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#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
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#define CONFIG_BOOTDELAY 5
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/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
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#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
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/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
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#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
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@ -112,7 +112,7 @@
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#define CONFIG_BOOTDELAY 5
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/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
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#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
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/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
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