Merge with git://www.denx.de/git/u-boot.git

2025-09-12 05:25:11 -04:00 · 2007-09-07 13:26:51 +01:00 · 2007-09-07 13:26:51 +01:00 · 470ffef72c
commit 470ffef72c
parent 80767a6cea a89cbbd27a
40 changed files with 2361 additions and 320 deletions
--- a/539
+++ b/539
@ -1,3 +1,542 @@
 commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3
 Author: stefano babic <sbabic@denx.de>
 Date:	Thu Aug 30 23:01:49 2007 +0200
    PXA270: Added support for TrizepsIV board.
    This patch add support for the Trizeps IV module (520Mhz).
    Signed-off-by: Stefano Babic <sbabic@denx.de>
 commit 80172c6181c912fbb34ea3ba0c22b232b419b47f
 Author: stefano babic <sbabic@denx.de>
 Date:	Thu Aug 30 22:57:04 2007 +0200
    PXA270: Add support for multiple serial ports.
    This patch adds support for multiple serial ports to the PXA target.
    FFUART, BTUART and STUART are supported.
    Signed-off-by: Stefano Babic <sbabic@denx.de>
 commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e
 Author: stefano babic <sbabic@denx.de>
 Date:	Thu Aug 30 22:48:47 2007 +0200
    PXA270: fix compile issue (invalid lvalue)
    Code is broken for PXA270 due to "invalid lvalue in assignment".
    This patch fix it in pxa-regs.h
    Signed-off-by: Stefano Babic <sbabic@denx.de>
 commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8
 Author: Jason Jin <Jason.jin@freescale.com>
 Date:	Thu Aug 30 18:19:05 2007 +0800
    Add BUILD_DIR support for bios emulator.
    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
 commit b4d8a55145442f136982634862341a3e02002bda
 Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
 Date:	Fri Aug 31 14:41:51 2007 +0900
    [MIPS] Remove inline asm string functions
    Stop using inline string functions on MIPS as other ARCHs do so,
    since the optimized inline asm versions are not small.
    This change is triggered by a following MIPS build error:
    common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init':
    common/exports.c:32: undefined reference to `strcmp'
    make: *** [u-boot] Error 1
    Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
 commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5
 Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
 Date:	Fri Aug 31 14:41:45 2007 +0900
    [MIPS] Update asm string header
    This patches contains several bugfixes and cleanups in the latest upstream:
     - Don't include linux/config.h
     - Remove buggy inline version of memscan.
     - Merge with Linux 2.6.11-rc3.
     - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4.
     - Goodbye mips64.	31704 lines of code bite the dust.
     - Replace extern inline with static inline.
     - Fix return value of strncpy.
     - Remove a bunch more "$1" clobbers.
    Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
 commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2
 Author: Bartlomiej Sieka <tur@semihalf.com>
 Date:	Tue Sep 4 17:31:22 2007 +0200
    Fix do_bootm_linux() so that multi-file images with FDT blob boot.
    Fix incorrect blob address calculation in do_bootm_linux() that prevents
    booting the kernel from a multi-file image (kernel + initrd + blob).
    Also, make minor updates to the U-Boot's output and to the coding style.
    Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
 commit 041a2554ad619e80dce520c1a33210affcb6a3f2
 Author: Gary Jennejohn <gary.jennejohn@freenet.de>
 Date:	Fri Aug 31 14:29:04 2007 +0200
    Add support for Sil680 IDE controller.
    o add drivers/sil680.c to support the Sil680 IDE-controller.
    o drivers/Makefile: add sil680.o.
    Signed-off-by: Gary Jennejohn <garyj@denx.de>
 commit e79021223bc339df655e360645a52c457a74b067
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Thu Sep 6 09:47:40 2007 -0600
    bootm/fdt: Only process the fdt if an fdt address was provided
    Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style
    kernels using the board info structure (instead of passing a device tree)
    This change allows the old style booting to be used if the fdt argument
    was not passed to 'bootm'.
    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
    Acked-by: Kim Phillips <kim.phillips@freescale.com>
 commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Thu Sep 6 09:46:23 2007 -0600
    Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT
    Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
    Tested on: lite5200b
    Note: the fixup functions have not been moved to a common place.  This
    patch is targeted for immediate merging as in solves a build issue, but
    the final name/location of the fixups is still subject to debate.  I
    propose to merge this now, and move the fixups in the next merge window
    to be usable by all targets.
    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 commit 41bb76e941929f54a73206fb132f7a4c275543a3
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Thu Sep 6 09:46:17 2007 -0600
    libfdt: add convenience function fdt_find_and_setprop()
    Given the path to a node, fdt_find_and_setprop() allows a property value
    to be set directly.
    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 commit 56a9270521baaa00e12639a978302a67f61ef060
 Author: Kumar Gala <galak@kernel.crashing.org>
 Date:	Thu Aug 30 16:18:18 2007 -0500
    Fix ULI RTC support on MPC8544 DS
    The RTC on the M1575 ULI chipset requires a dummy read before
    we are able to talk to the RTC.  We accomplish this by adding a
    second memory region to the PHB the ULI is on and read from it.
    The second region is added to maintain compatiabilty with Linux's
    view of the PCI memory map.
    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
 commit f75e89e9b5714db2b0e80074071dfbdd6f59488a
 Author: Ed Swarthout <Ed.Swarthout@freescale.com>
 Date:	Thu Aug 30 01:58:48 2007 -0500
    ft_board_setup update 85xx/86xx of pci/pcie bus-range property.
    pcie is now differentiated from pci.  Add 8641 bus-range updates.
    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
 commit 81b73dec16fd1227369a191e725e10044a9d56b8
 Author: Gary Jennejohn <garyj@denx.de>
 Date:	Fri Aug 31 15:21:46 2007 +0200
    ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
    The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
    set to non-zero, because it doesn't support MRM (memory-read-
    multiple) correctly. We now added the possibility to configure
    this register in the board config file, so that the default value
    of 8 can be overridden.
    Here the details of this patch:
    o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
      board-specific settings. As an example the sequoia board requires 0.
      Idea from Stefan Roese <sr@denx.de>.
    o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
      PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
    o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
      CFG_PCI_CACHE_LINE_SIZE to 0.
    Signed-off-by: Gary Jennejohn <garyj@denx.de>
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit 60174746c668b309378a91488dded898e9553eae
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Fri Aug 31 10:01:51 2007 +0200
    Fix TFTP OACK code for short packets.
    The old code had a loop limit overflow bug which caused a semi-
    infinite loop for small packets, because in "i<len-8", "i" was signed,
    but "len" was unsigned, and "len-8" became a huge number for small
    values of "len".
    This is a workaround which replaces broken commit 8f1bc284.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit ff13ac8c7bbebb238e339592de765c546dba1073
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Thu Aug 30 14:42:15 2007 +0200
    Backout commit 8f1bc284 as it causes TFTP to fail.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit 1900fbf255acba8b94fb442a16408ea85a1d46a6
 Author: Ed Swarthout <Ed.Swarthout@freescale.com>
 Date:	Thu Aug 30 02:26:17 2007 -0500
    Revert "Fix MPC8544DS PCIe3 scsi."
    This reverts commit 9468e680.
    Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient.
    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
 commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774
 Author: Grant Likely <grant.likely@secretlab.ca>
 Date:	Wed Aug 29 18:26:24 2007 -0600
    tftp: don't implicity trust the format of recevied packets
    The TFTP OACK code trusts that the incoming packet is formated as
    ASCII text and can be processed by string functions. It also has a
    loop limit overflow bug where if the packet length is less than 8, it
    ends up looping over *all* of memory to find the 'blksize' string.
    This patch solves the problem by forcing the packet to be null
    terminated and using strstr() to search for the sub string.
    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
 commit 2602a5c40ae37ab965a4e240854fdaffb51328a4
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Wed Aug 29 09:06:05 2007 -0500
    sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE
    this had slipped through the cracks, since the sbc board was added
    after I wrote the original patch to remove all these symbols, and
    before it was merged.
    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
 commit c5bded3c88e48ae648a75d357dc81a8255fa81f1
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Aug 29 14:05:30 2007 +0200
    Add mii_init() prototype
    to get rid of a *lot* of compiler warnings.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Aug 29 13:35:03 2007 +0200
    Disable network support on cmi_mpc5xx board
    ..because it caused compiler errors and there seems to be no
    board maintainer to take care of this.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit 9468e6804b7e25b0f6f52e53f47bce3175400a16
 Author: Kumar Gala <galak@kernel.crashing.org>
 Date:	Mon Aug 20 09:44:00 2007 -0500
    Fix MPC8544DS PCIe3 scsi.
    <ed.swarthout@freescale.com>
    The problem is pciauto_setup_device() getting called from fsl_pci_init.c
    is allocating memory space it doesn't need.
    Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
    Signed-off-by: Andy Fleming <afleming@freescale.com>
 commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a
 Author: Ed Swarthout <Ed.Swarthout@freescale.com>
 Date:	Tue Aug 21 09:38:59 2007 -0500
    8548cds fixes
    Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
    correct consoledev needed for linux boot.
    Standardize on fdt{file,addr} var to hold dtb file name.
    Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.
    Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
 commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933
 Author: Haiying Wang <Haiying.Wang@freescale.com>
 Date:	Thu Aug 23 15:20:54 2007 -0400
    Enable L2 cache for MPC8568MDS board
    The L2 cache size is 512KB for 8568, print out the correct informaiton.
    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
 commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b
 Author: Jason Jin <Jason.jin@freescale.com>
 Date:	Wed Aug 22 17:54:49 2007 +0800
    Remove the bios emulator binary files from MAI board
    Signed-off-by: Jason Jin <Jason.jin@freescale.com>
 commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Tue Aug 21 17:00:17 2007 -0500
    support board vendor-common makefiles
    if a board/$(VENDOR)/common/Makefile exists, build it.
    also add the first such case, board/freescale/common/Makefile, to
    handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
    dictated by board configuration.
    thusly get rid of alternate build dir errors such as:
    FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
    by putting the common/ mkdir command in its proper place (the common
    Makefile). Common bits from existing individual board Makefiles have
    been removed.
    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
 commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd
 Author: stefano babic <sbabic@denx.de>
 Date:	Tue Aug 21 15:52:33 2007 +0200
    Fix: TFTP is not working on little endian systems
    TFTP does not work anymore after multicast tftp
    patch was applied on little endian systems.
    This patch fix it.
    Signed-off-by: Stefano Babic <sbabic@denx.de>
 commit 5f470948570526e9186f053a3003da7719604e90
 Author: stefano babic <sbabic@denx.de>
 Date:	Tue Aug 21 15:50:33 2007 +0200
    Fix MAC address setting in DM9000 driver.
    The logic to check if there is a correct MAC address in the DM9000
    EEPROM, added in the last patch, is wrong. Now the MAC address is
    always taken from the environment, even if a suitable MAC is present
    in the EEPROM.
    Signed-off-by: Stefano Babic <sbabic@denx.de>
 commit 4a8527ef086ec7c89f40674ef024ae6f988a614a
 Author: Martin Krause <martin.krause@tqs.de>
 Date:	Tue Aug 21 12:40:34 2007 +0200
    MPC5xxx: fix some compiler warnings in USB code
    Fix the following warnings:
    - usb.c:xx: warning: function declaration isn't a prototype
    - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer
      from pointer wihtout a cast
    Signed-off-by: Martin Krause <martin.krase@tqs.de>
 commit 16e23c3f5dab6937f5109365416808c7f15c122b
 Author: Ed Swarthout <Ed.Swarthout@freescale.com>
 Date:	Mon Aug 20 23:55:33 2007 -0500
    fsl_pci_init - Remove self PCSRBAR allocation
    CPU physical address space was being wasted by allocating a
    PCSRBAR PCI inbound region to it's memory space.
    As a rule, PCSRBAR should be left alone since it does not affect
    transactions from self and other masters may have changed it.
    Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
 commit 0e700ce03a23bb1921149bc77008ace7103d5289
 Author: Martin Krause <martin.krause@tqs.de>
 Date:	Mon Aug 20 13:56:47 2007 +0200
    Fix compiler warning in include/s3c2410.h
    This patch fixes the "type qualifiers ignored on fuction return tpye"
    warning for include/s3c2410.h
    Signed-off-by: Martin Krause <martin.krause@tqs.de>
 commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea
 Author: Dirk Behme <dirk.behme@googlemail.com>
 Date:	Mon Aug 20 07:09:05 2007 +0200
    Fix compilation error for omap2420h4_config.
    omap2420h4 switched to cfi, so remove old (already disabled) flash.c
    and flash_probe() calls in env_flash.c.
    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
 commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Fri Aug 10 14:34:14 2007 -0500
    fdt: remove unused OF_FLAT_TREE_MAX_SIZE references
    and make some minor corrections to the FDT part of the README.
    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
 commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Wed Aug 29 01:32:05 2007 +0200
    Minor coding style cleanup.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3
 Author: Heiko Schocher <hs@pollux.denx.de>
 Date:	Tue Aug 28 17:40:33 2007 +0200
    [UC101] Fix: if no CF in the board, U-Boot resets sometimes.
    Signed-off-by: Heiko Schocher <hs@denx.de>
 commit f98984cb194bb34dbe1db9429d3b51133af30d07
 Author: Heiko Schocher <hs@pollux.denx.de>
 Date:	Tue Aug 28 17:39:14 2007 +0200
    IDE:	- make ide_inb () and ide_outb () "weak", so boards can
 	      define there own I/O functions.
 	      (Needed for the pcs440ep board).
 	    - The default I/O Functions are again 8 Bit accesses.
 	    - Added CONFIG_CMD_IDE for the pcs440ep Board.
    Signed-off-by: Heiko Schocher <hs@denx.de>
 commit 9c02defc29b57945b600714cf61ddfd02b02fb14
 Author: Yuri Tikhonov <yur@emcraft.com>
 Date:	Sat Aug 25 05:07:16 2007 +0200
    POST: limit memory test area to not touch global data anymore
    As experienced on lwmon5, on some boards the POST memory test can
    corrupt the global data buffer (bd). This patch fixes this issue
    by checking and limiting this area.
    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit 75e1a84d483e36be10e206e539b028c4889e1158
 Author: Stefan Roese <sr@denx.de>
 Date:	Fri Aug 24 15:41:42 2007 +0200
    ppc4xx: Add RTC POST test to lwmon5 board configuration
    Since this RTC POST test is taking quite a while to complete
    it's only initiated upon special keypress same as the complete
    memory POST.
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit d7bfa620037a6d2210159387571bdf93aa32c162
 Author: Stefan Roese <sr@denx.de>
 Date:	Fri Aug 24 15:19:10 2007 +0200
    ppc4xx: Change GPIO signal for watchdog triggering on lwmon5
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit c25dd8fc25e9ca3695db996a257d9ba4dab414db
 Author: Stefan Roese <sr@denx.de>
 Date:	Thu Aug 23 11:02:37 2007 +0200
    ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board
    This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
    board. Now the "eeprom" command can be used to read/write from/to this
    device. Additionally a new command was added "eepromwp" to en-/disable
    the write-protect of this 2nd EEPROM.
    The 1st EEPROM is not affected by this write-protect command.
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit c64fb30e4c5976007d56fc1789c7a0666082b536
 Author: Stefan Roese <sr@denx.de>
 Date:	Wed Aug 22 08:56:09 2007 +0200
    ppc4xx: Remove unused option CFG_INIT_RAM_OCM
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7
 Author: Stefan Roese <sr@denx.de>
 Date:	Tue Aug 21 16:27:57 2007 +0200
    ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)
    This patch adds support for the matrix keyboard on the lwmon5 board.
    Since the implementation in the dsPCI is kind of compatible with the
    "old" lwmon board, most of the code is copied from the lwmon
    board directory.
    Signed-off-by: Stefan Roese <sr@denx.de>
 commit 3e66c078003607a7d1d214c15a5f262bc1b4032f
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sun Aug 19 10:27:34 2007 +0200
    Fix some build errors.
    Signed-off-by: Wolfgang Denk <wd@denx.de>
 commit 05675735ef77dc23b5e0eb782bad1ff477b55e86
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat Aug 18 22:00:38 2007 +0200
    Update CHANGELOG.
 commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57
 Author: Kim Phillips <kim.phillips@freescale.com>
 Date:	Thu Aug 16 22:52:39 2007 -0500
--- a/3
+++ b/3
@ -2334,6 +2334,9 @@ scpu_config:    unconfig
 pxa255_idp_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
 trizepsiv_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
 wepep250_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa wepep250
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@ -126,6 +126,9 @@ tlbtab:
 	/* TLB-entry for peripherals */
 	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 	/* TLB-entry PCI IO Space - from sr@denx.de */
 	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 	tlbtab_end
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@ -542,7 +542,7 @@ ft_pci_setup(void *blob, bd_t *bd)
 #endif
 #ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@ -237,6 +237,6 @@ law_entry:
 	/* contains both PCIE3 MEM & IO space */
 	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
 	entry_end
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
@ -222,6 +223,11 @@ pci_init_board(void)
 		printf ("    PCIE3 on bus %02x - %02x\n",
 			hose->first_busno,hose->last_busno);
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
 		in_be32(CFG_PCIE3_MEM_BASE);
 	} else {
 		printf ("    PCIE3: disabled\n");
 	}
@ -516,8 +522,16 @@ ft_board_setup(void *blob, bd_t *bd)
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
 #ifdef CONFIG_PCI1
 	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 	}
 #endif
 #ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
@ -525,7 +539,7 @@ ft_board_setup(void *blob, bd_t *bd)
 	}
 #endif
 #ifdef CONFIG_PCIE2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
@ -533,7 +547,7 @@ ft_board_setup(void *blob, bd_t *bd)
 	}
 #endif
 #ifdef CONFIG_PCIE3
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@ -338,6 +338,22 @@ ft_board_setup(void *blob, bd_t *bd)
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
 #ifdef CONFIG_PCI1
 	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 	}
 #endif
 #ifdef CONFIG_PCI2
 	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
 	if (p != NULL) {
 		p[0] = 0;
 		p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 	}
 #endif
 }
 #endif
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@ -28,10 +28,7 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 #include <asm/processor.h>
-
+#include <libfdt.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 #endif
 #if defined(CONFIG_LITE5200B)
 #include "mt46v32m16.h"
@ -386,7 +383,7 @@ void ide_set_reset (int idereset)
 }
 #endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@ -28,11 +28,7 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 #include <asm/processor.h>
-
+#include <libfdt.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 #endif
 #define SDRAM_DDR	0
 #if 1
@ -308,7 +304,7 @@ void ide_set_reset (int idereset)
 }
 #endif
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@ -29,9 +29,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <miiphy.h>
-#if defined(CONFIG_OF_FLAT_TREE)
+#include <libfdt.h>
 #include <ft_build.h>
 #endif
 #if defined(CONFIG_STATUS_LED)
 #include <status_led.h>
@ -196,12 +194,12 @@ int checkboard(void)
 }
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 #if defined(CONFIG_STATUS_LED)
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@ -31,10 +31,7 @@
 #include <mpc5xxx.h>
 #include <pci.h>
 #include <asm/processor.h>
-
+#include <libfdt.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 #endif
 #ifdef CONFIG_VIDEO_SM501
 #include <sm501.h>
@ -780,9 +777,9 @@ int board_get_height (void)
 #endif /* CONFIG_VIDEO_SM501 */
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- a/board/trizepsiv/Makefile
+++ b/board/trizepsiv/Makefile
@ -0,0 +1,51 @@
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
 # published by the Free Software Foundation; either version 2 of
 # the License, or (at your option) any later version.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
 include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 COBJS	:= conxs.o eeprom.o
 SOBJS	:= lowlevel_init.o pxavoltage.o
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 clean:
 	rm -f $(SOBJS) $(OBJS)
 distclean:	clean
 	rm -f $(LIB) core *.bak .depend
 #########################################################################
 # defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 sinclude $(obj).depend
 #########################################################################
--- a/board/trizepsiv/config.mk
+++ b/board/trizepsiv/config.mk
@ -0,0 +1,3 @@
 TEXT_BASE =0xa1f00000
 # 0xa1700000
 #TEXT_BASE = 0
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@ -0,0 +1,146 @@
 /*
 * (C) Copyright 2007
 * Stefano Babic, DENX Gmbh, sbabic@denx.de
 *
 * (C) Copyright 2004
 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
 *
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 #include <common.h>
 #include <asm/arch/pxa-regs.h>
 DECLARE_GLOBAL_DATA_PTR;
 #define		RH_A_PSM	(1 << 8)	/* power switching mode */
 #define		RH_A_NPS	(1 << 9)	/* no power switching */
 extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
 /* ------------------------------------------------------------------------- */
 /*
 * Miscelaneous platform dependent initialisations
 */
 void usb_board_init(void)
 {
 	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
 	UHCHR |= UHCHR_FSBIR;
 	while (UHCHR & UHCHR_FSBIR);
 	UHCHR &= ~UHCHR_SSE;
 	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
 	/* Clear any OTG Pin Hold */
 	if (PSSR & PSSR_OTGPH)
 		PSSR |= PSSR_OTGPH;
 	UHCRHDA &= ~(RH_A_NPS);
 	UHCRHDA |= RH_A_PSM;
 	/* Set port power control mask bits, only 3 ports. */
 	UHCRHDB |= (0x7<<17);
 }
 void usb_board_init_fail(void)
 {
 	return;
 }
 void usb_board_stop(void)
 {
 	UHCHR |= UHCHR_FHR;
 	udelay(11);
 	UHCHR &= ~UHCHR_FHR;
 	UHCCOMS |= 1;
 	udelay(10);
 	CKEN &= ~CKEN10_USBHOST;
 	puts("Called USB STOP\n");
 	return;
 }
 int board_init (void)
 {
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 	/* arch number of ConXS Board */
 	gd->bd->bi_arch_number = 776;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0xa000003c;
 	return 0;
 }
 int board_late_init(void)
 {
 #if defined(CONFIG_SERIAL_MULTI)
 	char *console=getenv("boot_console");
 	if ((strcmp(console,"serial_btuart") == 0) ||
 		(strcmp(console,"serial_stuart") == 0) ||
 		(strcmp(console,"serial_ffuart") == 0)) {
 			setenv("stdout",console);
 			setenv("stdin", console);
 			setenv("stderr",console);
 	} else {
 		setenv("stdout", "serial");
 		setenv("stdin", "serial");
 		setenv("stderr", "serial");
 	}
 #endif
 	return 0;
 }
 struct serial_device *default_serial_console (void)
 {
 	return &serial_ffuart_device;
 }
 int dram_init (void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 	return 0;
 }
--- a/board/trizepsiv/eeprom.c
+++ b/board/trizepsiv/eeprom.c
@ -0,0 +1,85 @@
 /*
 * (C) Copyright 2007
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 #include <common.h>
 #include <command.h>
 static unsigned char srom[128];
 extern u16 read_srom_word(int);
 extern void write_srom_word(int offset, u16 val);
 static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
 	int i;
 	for (i=0; i < 0x40; i++) {
 		if (!(i % 0x10))
 			printf("\n%08lx:", i);
 		printf(" %04x", read_srom_word(i));
 	}
 	printf ("\n");
 	return (0);
 }
 static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
 	int offset,value;
 	if (argc < 4) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 	offset=simple_strtoul(argv[2],NULL,16);
 	value=simple_strtoul(argv[3],NULL,16);
 	if (offset > 0x40) {
 		printf("Wrong offset : 0x%x\n",offset);
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 	write_srom_word(offset, value);
 	return (0);
 }
 int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
 	if (argc < 2) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 	if (strcmp (argv[1],"read") == 0) {
 		return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
 	} else if (strcmp (argv[1],"write") == 0) {
 		return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
 	} else {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 }
 U_BOOT_CMD(
 	dm9000ee,4,1,do_dm9000_eeprom,
 	"dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
 	"\ndm9000ee write <word offset> <value> \n"
 	"\tdm9000ee read \n"
 	"\tword:\t\t00-02 : MAC Address\n"
 	"\t\t\t03-07 : DM9000 Configuration\n"
 	"\t\t\t08-63 : User data\n");
--- a/board/trizepsiv/lowlevel_init.S
+++ b/board/trizepsiv/lowlevel_init.S
@ -0,0 +1,503 @@
 /*
 * This was originally from the Lubbock u-boot port.
 *
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 #include <config.h>
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 /* wait for coprocessor write complete */
   .macro CPWAIT reg
   mrc	p15,0,\reg,c2,c0,0
   mov	\reg,\reg
   sub	pc,pc,#4
   .endm
 /*
 *	Memory setup
 */
 .globl lowlevel_init
 lowlevel_init:
 	/* Set up GPIO pins first ----------------------------------------- */
 	ldr		r0,	=GPSR0
 	ldr		r1,	=CFG_GPSR0_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPSR1
 	ldr		r1,	=CFG_GPSR1_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPSR2
 	ldr		r1,	=CFG_GPSR2_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPSR3
 	ldr		r1,	=CFG_GPSR3_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPCR0
 	ldr		r1,	=CFG_GPCR0_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPCR1
 	ldr		r1,	=CFG_GPCR1_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPCR2
 	ldr		r1,	=CFG_GPCR2_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPCR3
 	ldr		r1,	=CFG_GPCR3_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GRER0
 	ldr		r1,	=CFG_GRER0_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GRER1
 	ldr		r1,	=CFG_GRER1_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GRER2
 	ldr		r1,	=CFG_GRER2_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GRER3
 	ldr		r1,	=CFG_GRER3_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GFER0
 	ldr		r1,	=CFG_GFER0_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GFER1
 	ldr		r1,	=CFG_GFER1_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GFER2
 	ldr		r1,	=CFG_GFER2_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GFER3
 	ldr		r1,	=CFG_GFER3_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPDR0
 	ldr		r1,	=CFG_GPDR0_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPDR1
 	ldr		r1,	=CFG_GPDR1_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPDR2
 	ldr		r1,	=CFG_GPDR2_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GPDR3
 	ldr		r1,	=CFG_GPDR3_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR0_L
 	ldr		r1,	=CFG_GAFR0_L_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR0_U
 	ldr		r1,	=CFG_GAFR0_U_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR1_L
 	ldr		r1,	=CFG_GAFR1_L_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR1_U
 	ldr		r1,	=CFG_GAFR1_U_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR2_L
 	ldr		r1,	=CFG_GAFR2_L_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR2_U
 	ldr		r1,	=CFG_GAFR2_U_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR3_L
 	ldr		r1,	=CFG_GAFR3_L_VAL
 	str		r1,   [r0]
 	ldr		r0,	=GAFR3_U
 	ldr		r1,	=CFG_GAFR3_U_VAL
 	str		r1,   [r0]
 	ldr		r0,	=PSSR		/* enable GPIO pins */
 	ldr		r1,	=CFG_PSSR_VAL
 	str		r1,   [r0]
 	/* ---------------------------------------------------------------- */
 	/* Enable memory interface					    */
 	/*								    */
 	/* The sequence below is based on the recommended init steps	    */
 	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
 	/* Chapter 10.							    */
 	/* ---------------------------------------------------------------- */
 	/* ---------------------------------------------------------------- */
 	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
 	/*	   clocks to settle. Only necessary after hard reset...	    */
 	/*	   FIXME: can be optimized later			    */
 	/* ---------------------------------------------------------------- */
 	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
 	mov r2, #0
 	str r2, [r3]
 	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
 					/* so 0x300 should be plenty	    */
 1:
 	ldr r2, [r3]
 	cmp r4, r2
 	bgt 1b
 mem_init:
 	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
 	/* ---------------------------------------------------------------- */
 	/* Step 2a: Initialize Asynchronous static memory controller	    */
 	/* ---------------------------------------------------------------- */
 	/* MSC registers: timing, bus width, mem type			    */
 	/* MSC0: nCS(0,1)						    */
 	ldr	r2,   =CFG_MSC0_VAL
 	str	r2,   [r1, #MSC0_OFFSET]
 	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
 						/* that data latches	    */
 	/* MSC1: nCS(2,3)						    */
 	ldr	r2,  =CFG_MSC1_VAL
 	str	r2,  [r1, #MSC1_OFFSET]
 	ldr	r2,  [r1, #MSC1_OFFSET]
 	/* MSC2: nCS(4,5)						    */
 	ldr	r2,  =CFG_MSC2_VAL
 	str	r2,  [r1, #MSC2_OFFSET]
 	ldr	r2,  [r1, #MSC2_OFFSET]
 	/* ---------------------------------------------------------------- */
 	/* Step 2b: Initialize Card Interface				    */
 	/* ---------------------------------------------------------------- */
 	/* MECR: Memory Expansion Card Register				    */
 	ldr	r2,  =CFG_MECR_VAL
 	str	r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 	/* MCMEM0: Card Interface slot 0 timing				    */
 	ldr	r2,  =CFG_MCMEM0_VAL
 	str	r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 	/* MCMEM1: Card Interface slot 1 timing				    */
 	ldr	r2,  =CFG_MCMEM1_VAL
 	str	r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
 	ldr	r2,  =CFG_MCATT0_VAL
 	str	r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
 	ldr	r2,  =CFG_MCATT1_VAL
 	str	r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
 	ldr	r2,  =CFG_MCIO0_VAL
 	str	r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
 	ldr	r2,  =CFG_MCIO1_VAL
 	str	r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 	/* ---------------------------------------------------------------- */
 	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
 	/* ---------------------------------------------------------------- */
 	ldr	r2,  =CFG_FLYCNFG_VAL
 	str	r2,  [r1, #FLYCNFG_OFFSET]
 	str	r2,	[r1, #FLYCNFG_OFFSET]
 	/* ---------------------------------------------------------------- */
 	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
 	/* ---------------------------------------------------------------- */
 	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
 	/* this to power on defaults + DRI field.			    */
 	ldr	r4,	[r1, #MDREFR_OFFSET]
 	ldr	r2,	=0xFFF
 	bic	r4,	r4, r2
 	ldr	r3,	=CFG_MDREFR_VAL
 	and	r3,	r3,  r2
 	orr	r4,	r4, r3
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
 	orr	r4,  r4, #MDREFR_K0RUN
 	orr	r4,  r4, #MDREFR_K0DB4
 	orr	r4,  r4, #MDREFR_K0FREE
 	orr	r4,  r4, #MDREFR_K0DB2
 	orr	r4,  r4, #MDREFR_K1DB2
 	bic	r4,  r4, #MDREFR_K1FREE
 	bic	r4,  r4, #MDREFR_K2FREE
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
 	ldr	r4,  [r1, #MDREFR_OFFSET]
 	/* Note: preserve the mdrefr value in r4			    */
 	/* ---------------------------------------------------------------- */
 	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
 	/* ---------------------------------------------------------------- */
 	/* Initialize SXCNFG register. Assert the enable bits		    */
 	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
 	/* synchronous static memory. Note that SXLCR need not be written   */
 	/* at this time.						    */
 	ldr	r2,  =CFG_SXCNFG_VAL
 	str	r2,  [r1, #SXCNFG_OFFSET]
 	/* ---------------------------------------------------------------- */
 	/* Step 4: Initialize SDRAM					    */
 	/* ---------------------------------------------------------------- */
 	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
 	orr	r4, r4, #MDREFR_K1RUN
 	bic	r4, r4, #MDREFR_K2DB2
 	str	r4, [r1, #MDREFR_OFFSET]
 	ldr	r4, [r1, #MDREFR_OFFSET]
 	bic	r4, r4, #MDREFR_SLFRSH
 	str	r4, [r1, #MDREFR_OFFSET]
 	ldr	r4, [r1, #MDREFR_OFFSET]
 	orr	r4, r4, #MDREFR_E1PIN
 	str	r4, [r1, #MDREFR_OFFSET]
 	ldr	r4, [r1, #MDREFR_OFFSET]
 	nop
 	nop
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*	    configure but not enable each SDRAM partition pair.	    */
 	ldr	r4,	=CFG_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
 	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
 	ldr	r4,	[r1, #MDCNFG_OFFSET]
 	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
 	/*	    100..200 µsec.					    */
 	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
 	mov r2, #0
 	str r2, [r3]
 	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
 					/* so 0x300 should be plenty	    */
 1:
 	    ldr r2, [r3]
 	    cmp r4, r2
 	    bgt 1b
 	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
 	/*	    attempting non-burst read or write accesses to disabled */
 	/*	    SDRAM, as commonly specified in the power up sequence   */
 	/*	    documented in SDRAM data sheets. The address(es) used   */
 	/*	    for this purpose must not be cacheable.		    */
 	ldr	r3,	=CFG_DRAM_BASE
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
 	/* Step 4g: Write MDCNFG with enable bits asserted		    */
 	/*	    (MDCNFG:DEx set to 1).				    */
 	ldr	r3,	[r1, #MDCNFG_OFFSET]
 	mov	r4, r3
 	orr	r3,	r3,	#MDCNFG_DE0
 	str	r3,	[r1, #MDCNFG_OFFSET]
 	mov	r0, r3
 	/* Step 4h: Write MDMRS.					    */
 	ldr	r2,  =CFG_MDMRS_VAL
 	str	r2,  [r1, #MDMRS_OFFSET]
 	/* enable APD */
 	ldr	r3,  [r1, #MDREFR_OFFSET]
 	orr	r3,  r3,  #MDREFR_APD
 	str	r3,  [r1, #MDREFR_OFFSET]
 	/* We are finished with Intel's memory controller initialisation    */
 setvoltage:
 	mov	r10,	lr
 	bl	initPXAvoltage	/* In case the board is rebooting with a    */
 	mov	lr,	r10	/* low voltage raise it up to a good one.   */
 #if 1
 	b initirqs
 #endif
 wakeup:
 	/* Are we waking from sleep? */
 	ldr	r0,	=RCSR
 	ldr	r1,	[r0]
 	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
 	str	r1,	[r0]
 	teq	r1,	#RCSR_SMR
 	bne	initirqs
 	ldr	r0,	=PSSR
 	mov	r1,	#PSSR_PH
 	str	r1,	[r0]
 	/* if so, resume at PSPR */
 	ldr	r0,	=PSPR
 	ldr	r1,	[r0]
 	mov	pc,	r1
 	/* ---------------------------------------------------------------- */
 	/* Disable (mask) all interrupts at interrupt controller	    */
 	/* ---------------------------------------------------------------- */
 initirqs:
 	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
 	ldr	r2,  =ICLR
 	str	r1,  [r2]
 	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
 	str	r1,  [r2]
 	/* ---------------------------------------------------------------- */
 	/* Clock initialisation						    */
 	/* ---------------------------------------------------------------- */
 initclks:
 	/* Disable the peripheral clocks, and set the core clock frequency  */
 	/* Turn Off on-chip peripheral clocks (except for memory)	    */
 	/* for re-configuration.					    */
 	ldr	r1,  =CKEN
 	ldr	r2,  =CFG_CKEN
 	str	r2,  [r1]
 	/* ... and write the core clock config register			    */
 	ldr	r2,  =CFG_CCCR
 	ldr	r1,  =CCCR
 	str	r2,  [r1]
 	/* Turn on turbo mode */
 	mrc	p14, 0, r2, c6, c0, 0
 	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
 	mcr	p14, 0, r2, c6, c0, 0
 	/* Re-write MDREFR */
 	ldr	r1, =MEMC_BASE
 	ldr	r2, [r1, #MDREFR_OFFSET]
 	str	r2, [r1, #MDREFR_OFFSET]
 #ifdef RTC
 	/* enable the 32Khz oscillator for RTC and PowerManager		    */
 	ldr	r1,  =OSCC
 	mov	r2,  #OSCC_OON
 	str	r2,  [r1]
 	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
 	/* has settled.							    */
 60:
 	ldr	r2, [r1]
 	ands	r2, r2, #1
 	beq	60b
 #else
 #error "RTC not defined"
 #endif
 	/* Interrupt init: Mask all interrupts				    */
    ldr r0, =ICMR /* enable no sources */
 	mov r1, #0
    str r1, [r0]
 	/* FIXME */
 #ifdef NODEBUG
 	/*Disable software and data breakpoints */
 	mov	r0,#0
 	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
 	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
 	mcr	p15,0,r0,c14,c4,0  /* dbcon */
 	/*Enable all debug functionality */
 	mov	r0,#0x80000000
 	mcr	p14,0,r0,c10,c0,0  /* dcsr */
 #endif
 	/* ---------------------------------------------------------------- */
 	/* End lowlevel_init							    */
 	/* ---------------------------------------------------------------- */
 endlowlevel_init:
 	mov	pc, lr
--- a/board/trizepsiv/pxavoltage.S
+++ b/board/trizepsiv/pxavoltage.S
@ -0,0 +1,29 @@
 /*
 * (C) Copyright 2007
 * Stefano Babic, DENX Gmbh, sbabic@denx.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 #include <asm/arch/pxa-regs.h>
 		.global	initPXAvoltage
 initPXAvoltage:
 		mov	pc, lr
--- a/board/trizepsiv/u-boot.lds
+++ b/board/trizepsiv/u-boot.lds
@ -0,0 +1,56 @@
 /*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
 {
 	. = 0x00000000;
 	. = ALIGN(4);
 	.text      :
 	{
 	  cpu/pxa/start.o	(.text)
 	  *(.text)
 	}
 	. = ALIGN(4);
 	.rodata : { *(.rodata) }
 	. = ALIGN(4);
 	.data : { *(.data) }
 	. = ALIGN(4);
 	.got : { *(.got) }
 	. = .;
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
 	. = ALIGN(4);
 	__bss_start = .;
 	.bss : { *(.bss) }
 	_end = .;
 }
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@ -817,27 +817,32 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		int i;
 		/* skip kernel length, initrd length, and terminator */
-		of_data = (ulong)(&len_ptr[3]);
+		of_flat_tree = (char *)(&len_ptr[3]);
 		/* skip any additional image length fields */
 		for (i=2; len_ptr[i]; ++i)
-			of_data += 4;
+			of_flat_tree += 4;
 		/* add kernel length, and align */
-		of_data += ntohl(len_ptr[0]);
+		of_flat_tree += ntohl(len_ptr[0]);
 		if (tail) {
-			of_data += 4 - tail;
+			of_flat_tree += 4 - tail;
 		}
 		/* add initrd length, and align */
 		tail = ntohl(len_ptr[1]) % 4;
-		of_data += ntohl(len_ptr[1]);
+		of_flat_tree += ntohl(len_ptr[1]);
 		if (tail) {
-			of_data += 4 - tail;
+			of_flat_tree += 4 - tail;
 		}
 		/* move the blob if it is in flash (set of_data to !null) */
 		if (addr2info ((ulong)of_flat_tree) != NULL)
 			of_data = (ulong)of_flat_tree;
 #if defined(CONFIG_OF_FLAT_TREE)
-		if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
+		if (*((ulong *)(of_flat_tree)) != OF_DT_HEADER) {
 #else
-		if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
+		if (fdt_check_header (of_flat_tree) != 0) {
 #endif
 			puts ("ERROR: image is not a fdt - "
 				"must RESET the board to recover.\n");
@ -845,9 +850,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		}
 #if defined(CONFIG_OF_FLAT_TREE)
-		if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
+		if (((struct boot_param_header *)of_flat_tree)->totalsize !=
 			ntohl (len_ptr[2])) {
 #else
-		if (be32_to_cpu(fdt_totalsize(of_data)) !=  ntohl(len_ptr[2])) {
+		if (be32_to_cpu (fdt_totalsize (of_flat_tree)) !=
 			ntohl(len_ptr[2])) {
 #endif
 			puts ("ERROR: fdt size != image size - "
 				"must RESET the board to recover.\n");
@ -957,11 +964,13 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 				"must RESET the board to recover.\n");
 			do_reset (cmdtp, flag, argc, argv);
 		}
 		puts ("OK\n");
 	}
 	/*
 	 * Add the chosen node if it doesn't exist, add the env and bd_t
 	 * if the user wants it (the logic is in the subroutines).
 	 */
 	if (of_flat_tree) {
 		if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
 			puts ("ERROR: /chosen node create failed - "
 				"must RESET the board to recover.\n");
@ -985,6 +994,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		/* Call the board-specific fixup routine */
 		ft_board_setup(of_flat_tree, gd->bd);
 #endif
 	}
 #endif /* CONFIG_OF_LIBFDT */
 #if defined(CONFIG_OF_FLAT_TREE)
 #ifdef CFG_BOOTMAPSZ
@ -1011,6 +1021,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		printf ("   Loading Device Tree to %08lx, end %08lx ... ",
 			of_start, of_start + of_len - 1);
 		memmove ((void *)of_start, (void *)of_data, of_len);
 		puts ("OK\n");
 	}
 	/*
 	 * Create the /chosen node and modify the blob with board specific
--- a/common/serial.c
+++ b/common/serial.c
@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct serial_device *serial_devices = NULL;
 static struct serial_device *serial_current = NULL;
-#ifndef CONFIG_LWMON
+#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X)
 struct serial_device *default_serial_console (void)
 {
 #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
@ -65,7 +65,7 @@ struct serial_device *default_serial_console (void)
 }
 #endif
-static int serial_register (struct serial_device *dev)
+int serial_register (struct serial_device *dev)
 {
 	dev->init += gd->reloc_off;
 	dev->setbrg += gd->reloc_off;
@ -110,6 +110,15 @@ void serial_initialize (void)
 	serial_register(&eserial4_device);
 #endif
 #endif /* CFG_NS16550_SERIAL */
 #if defined (CONFIG_FFUART)
 	serial_register(&serial_ffuart_device);
 #endif
 #if defined (CONFIG_BTUART)
 	serial_register(&serial_btuart_device);
 #endif
 #if defined (CONFIG_STUART)
 	serial_register(&serial_stuart_device);
 #endif
 	serial_assign (default_serial_console ()->name);
 }
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@ -29,10 +29,12 @@
 #include <watchdog.h>
 #include <command.h>
 #include <mpc5xxx.h>
 #include <asm/io.h>
 #include <asm/processor.h>
-#if defined(CONFIG_OF_FLAT_TREE)
+#if defined(CONFIG_OF_LIBFDT)
-#include <ft_build.h>
+#include <libfdt.h>
 #include <libfdt_env.h>
 #endif
 DECLARE_GLOBAL_DATA_PTR;
@ -111,29 +113,43 @@ unsigned long get_tbclk (void)
 /* ------------------------------------------------------------------------- */
-#ifdef CONFIG_OF_FLAT_TREE
+#ifdef CONFIG_OF_LIBFDT
-void
+static void do_fixup(void *fdt, const char *node, const char *prop,
-ft_cpu_setup(void *blob, bd_t *bd)
+		     const void *val, int len, int create)
 {
-	u32 *p;
+#if defined(DEBUG)
-	int len;
+	int i;
 	debug("Updating property '%s/%s' = ", node, prop);
 	for (i = 0; i < len; i++)
 		debug(" %.2x", *(u8*)(val+i));
 	debug("\n");
 #endif
 	int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create);
 	if (rc)
 		printf("Unable to update property %s:%s, err=%s\n",
 		       node, prop, fdt_strerror(rc));
 }
-	/* Core XLB bus frequency */
+static void do_fixup_u32(void *fdt, const char *node, const char *prop,
-	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+			 u32 val, int create)
-	if (p != NULL)
+{
-		*p = cpu_to_be32(bd->bi_busfreq);
+	val = cpu_to_fdt32(val);
 	do_fixup(fdt, node, prop, &val, sizeof(val), create);
 }
-	/* SOC peripherals use the IPB bus frequency */
+void ft_cpu_setup(void *blob, bd_t *bd)
-	p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
+{
-	if (p != NULL)
+	int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4;
-		*p = cpu_to_be32(bd->bi_ipbfreq);
+	char * cpu_path = "/cpus/" OF_CPU;
 	char * eth_path = "/" OF_SOC "/ethernet@3000";
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
+	do_fixup_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
-	if (p != NULL)
+	do_fixup_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
-		memcpy(p, bd->bi_enetaddr, 6);
+	do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
-
+	do_fixup_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len);
+	do_fixup_u32(blob, "/" OF_SOC, "system-frequency",
-	if (p != NULL)
+			bd->bi_busfreq*div, 1);
-		memcpy(p, bd->bi_enetaddr, 6);
+	do_fixup(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0);
 	do_fixup(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
 }
 #endif
--- a/cpu/pxa/serial.c
+++ b/cpu/pxa/serial.c
@ -30,11 +30,28 @@
 #include <common.h>
 #include <watchdog.h>
 #include <serial.h>
 #include <asm/arch/pxa-regs.h>
 DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+#define FFUART	0
 #define BTUART	1
 #define STUART	2
 #ifndef CONFIG_SERIAL_MULTI
 #if defined (CONFIG_FFUART)
 #define UART_INDEX	FFUART
 #elif defined (CONFIG_BTUART)
 #define UART_INDEX	BTUART
 #elif defined (CONFIG_STUART)
 #define UART_INDEX	STUART
 #else
 #error "Bad: you didn't configure serial ..."
 #endif
 #endif
 void pxa_setbrg_dev (unsigned int uart_index)
 {
 	unsigned int quot = 0;
@ -53,7 +70,8 @@ void serial_setbrg (void)
 	else
 		hang ();
-#ifdef CONFIG_FFUART
+	switch (uart_index) {
 		case FFUART:
 #ifdef CONFIG_CPU_MONAHANS
 			CKENA |= CKENA_22_FFUART;
 #else
@ -70,8 +88,9 @@ void serial_setbrg (void)
 			FFLCR = LCR_WLS0 | LCR_WLS1;
 			FFIER = IER_UUE;	/* Enable FFUART */
 		break;
-#elif defined(CONFIG_BTUART)
+		case BTUART:
 #ifdef CONFIG_CPU_MONAHANS
 			CKENA |= CKENA_21_BTUART;
 #else
@ -89,7 +108,9 @@ void serial_setbrg (void)
 			BTIER = IER_UUE;	/* Enable BFUART */
-#elif defined(CONFIG_STUART)
+		break;
 		case STUART:
 #ifdef CONFIG_CPU_MONAHANS
 			CKENA |= CKENA_23_STUART;
 #else
@ -106,10 +127,11 @@ void serial_setbrg (void)
 			STLCR = LCR_WLS0 | LCR_WLS1;
 			STIER = IER_UUE;			/* Enable STUART */
 			break;
-#else
+		default:
-#error "Bad: you didn't configure serial ..."
+			hang();
-#endif
+	}
 }
@ -118,9 +140,9 @@ void serial_setbrg (void)
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 *
 */
-int serial_init (void)
+int pxa_init_dev (unsigned int uart_index)
 {
-	serial_setbrg ();
+	pxa_setbrg_dev (uart_index);
 	return (0);
 }
@ -129,26 +151,32 @@ int serial_init (void)
 /*
 * Output a single byte to the serial port.
 */
-void serial_putc (const char c)
+void pxa_putc_dev (unsigned int uart_index,const char c)
 {
-#ifdef CONFIG_FFUART
+	switch (uart_index) {
 		case FFUART:
 		/* wait for room in the tx FIFO on FFUART */
 			while ((FFLSR & LSR_TEMT) == 0)
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			FFTHR = c;
-#elif defined(CONFIG_BTUART)
+			break;
 		case BTUART:
 			while ((BTLSR & LSR_TEMT ) == 0 )
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			BTTHR = c;
-#elif defined(CONFIG_STUART)
+			break;
 		case STUART:
 			while ((STLSR & LSR_TEMT ) == 0 )
 				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			STTHR = c;
-#endif
+			break;
 	}
 	/* If \n, also do \r */
 	if (c == '\n')
-		serial_putc ('\r');
+		pxa_putc_dev (uart_index,'\r');
 }
 /*
@ -156,15 +184,17 @@ void serial_putc (const char c)
 * otherwise. When the function is succesfull, the character read is
 * written into its argument c.
 */
-int serial_tstc (void)
+int pxa_tstc_dev (unsigned int uart_index)
 {
-#ifdef CONFIG_FFUART
+	switch (uart_index) {
 		case FFUART:
 			return FFLSR & LSR_DR;
-#elif defined(CONFIG_BTUART)
+		case BTUART:
 			return BTLSR & LSR_DR;
-#elif defined(CONFIG_STUART)
+		case STUART:
 			return STLSR & LSR_DR;
-#endif
+	}
 	return -1;
 }
 /*
@ -172,27 +202,184 @@ int serial_tstc (void)
 * otherwise. When the function is succesfull, the character read is
 * written into its argument c.
 */
-int serial_getc (void)
+int pxa_getc_dev (unsigned int uart_index)
 {
-#ifdef CONFIG_FFUART
+	switch (uart_index) {
 		case FFUART:
 			while (!(FFLSR & LSR_DR))
 			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			return (char) FFRBR & 0xff;
-#elif defined(CONFIG_BTUART)
+
 		case BTUART:
 			while (!(BTLSR & LSR_DR))
 			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			return (char) BTRBR & 0xff;
-#elif defined(CONFIG_STUART)
+		case STUART:
 			while (!(STLSR & LSR_DR))
 			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 			return (char) STRBR & 0xff;
-#endif
+	}
 	return -1;
 }
 void
-serial_puts (const char *s)
+pxa_puts_dev (unsigned int uart_index,const char *s)
 {
 	while (*s) {
-		serial_putc (*s++);
+		pxa_putc_dev (uart_index,*s++);
 	}
 }
 #if defined (CONFIG_FFUART)
 static int ffuart_init(void)
 {
 	return pxa_init_dev(FFUART);
 }
 static void ffuart_setbrg(void)
 {
 	return pxa_setbrg_dev(FFUART);
 }
 static void ffuart_putc(const char c)
 {
 	return pxa_putc_dev(FFUART,c);
 }
 static void ffuart_puts(const char *s)
 {
 	return pxa_puts_dev(FFUART,s);
 }
 static int ffuart_getc(void)
 {
 	return pxa_getc_dev(FFUART);
 }
 static int ffuart_tstc(void)
 {
 	return pxa_tstc_dev(FFUART);
 }
 struct serial_device serial_ffuart_device =
 {
 	"serial_ffuart",
 	"PXA",
 	ffuart_init,
 	ffuart_setbrg,
 	ffuart_getc,
 	ffuart_tstc,
 	ffuart_putc,
 	ffuart_puts,
 };
 #endif
 #if defined (CONFIG_BTUART)
 static int btuart_init(void)
 {
 	return pxa_init_dev(BTUART);
 }
 static void btuart_setbrg(void)
 {
 	return pxa_setbrg_dev(BTUART);
 }
 static void btuart_putc(const char c)
 {
 	return pxa_putc_dev(BTUART,c);
 }
 static void btuart_puts(const char *s)
 {
 	return pxa_puts_dev(BTUART,s);
 }
 static int btuart_getc(void)
 {
 	return pxa_getc_dev(BTUART);
 }
 static int btuart_tstc(void)
 {
 	return pxa_tstc_dev(BTUART);
 }
 struct serial_device serial_btuart_device =
 {
 	"serial_btuart",
 	"PXA",
 	btuart_init,
 	btuart_setbrg,
 	btuart_getc,
 	btuart_tstc,
 	btuart_putc,
 	btuart_puts,
 };
 #endif
 #if defined (CONFIG_STUART)
 static int stuart_init(void)
 {
 	return pxa_init_dev(STUART);
 }
 static void stuart_setbrg(void)
 {
 	return pxa_setbrg_dev(STUART);
 }
 static void stuart_putc(const char c)
 {
 	return pxa_putc_dev(STUART,c);
 }
 static void stuart_puts(const char *s)
 {
 	return pxa_puts_dev(STUART,s);
 }
 static int stuart_getc(void)
 {
 	return pxa_getc_dev(STUART);
 }
 static int stuart_tstc(void)
 {
 	return pxa_tstc_dev(STUART);
 }
 struct serial_device serial_stuart_device =
 {
 	"serial_stuart",
 	"PXA",
 	stuart_init,
 	stuart_setbrg,
 	stuart_getc,
 	stuart_tstc,
 	stuart_putc,
 	stuart_puts,
 };
 #endif
 #ifndef CONFIG_SERIAL_MULTI
 inline int serial_init(void) {
 	return (pxa_init_dev(UART_INDEX));
 }
 void serial_setbrg(void) {
 	pxa_setbrg_dev(UART_INDEX);
 }
 int serial_getc(void) {
 	return(pxa_getc_dev(UART_INDEX));
 }
 int serial_tstc(void) {
 	return(pxa_tstc_dev(UART_INDEX));
 }
 void serial_putc(const char c) {
 	pxa_putc_dev(UART_INDEX,c);
 }
 void serial_puts(const char *s) {
 	pxa_puts_dev(UART_INDEX,s);
 }
 #endif	/* CONFIG_SERIAL_MULTI */
--- a/drivers/Makefile
+++ b/drivers/Makefile
@ -43,7 +43,7 @@ COBJS	= 3c589.o 5701rls.o ali512x.o at45.o ata_piix.o atmel_usart.o \
 	  sed13806.o sed156x.o \
 	  serial.o serial_max3100.o \
 	  serial_pl010.o serial_pl011.o serial_xuartlite.o \
-	  sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
+	  sil680.o sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
 	  status_led.o sym53c8xx.o systemace.o ahci.o \
 	  ti_pci1410a.o tigon3.o tsec.o \
 	  tsi108_eth.o tsi108_i2c.o tsi108_pci.o \
--- a/drivers/bios_emulator/Makefile
+++ b/drivers/bios_emulator/Makefile
@ -2,9 +2,11 @@ include $(TOPDIR)/config.mk
 LIB := $(obj)libatibiosemu.a
-X86DIR  = ./x86emu
+X86DIR  = x86emu
-OBJS	= atibios.o biosemu.o besys.o bios.o  \
+$(shell mkdir -p $(obj)$(X86DIR))
 COBJS	= atibios.o biosemu.o besys.o bios.o \
 	$(X86DIR)/decode.o \
 	$(X86DIR)/ops2.o \
 	$(X86DIR)/ops.o \
@ -12,19 +14,24 @@ OBJS	= atibios.o biosemu.o besys.o bios.o  \
 	$(X86DIR)/sys.o \
 	$(X86DIR)/debug.o
-CFLAGS += -I. -I./include  -I$(X86DIR) -I$(TOPDIR)/include \
+SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
 	-D__PPC__  -D__BIG_ENDIAN__
 CFLAGS += $(EXTRA_CFLAGS)
 HOST_CFLAGS += $(EXTRA_CFLAGS)
 all:	$(LIB)
-$(LIB): $(OBJS)
+$(LIB): $(obj).depend $(OBJS)
-	$(AR) crv $@ $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 #########################################################################
-.depend:	Makefile $(OBJS:.o=.c)
+include $(SRCTREE)/rules.mk
 		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
-sinclude .depend
+sinclude $(obj).depend
 #########################################################################
--- a/drivers/dm9000x.c
+++ b/drivers/dm9000x.c
@ -99,7 +99,7 @@ void eth_halt(void);
 static int dm9000_probe(void);
 static u16 phy_read(int);
 static void phy_write(int, u16);
-static u16 read_srom_word(int);
+u16 read_srom_word(int);
 static u8 DM9000_ior(int);
 static void DM9000_iow(int reg, u8 value);
@ -537,7 +537,7 @@ eth_rx(void)
 /*
  Read a word data from SROM
 */
-static u16
+u16
 read_srom_word(int offset)
 {
 	DM9000_iow(DM9000_EPAR, offset);
@ -547,6 +547,18 @@ read_srom_word(int offset)
 	return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
 }
 void
 write_srom_word(int offset, u16 val)
 {
 	DM9000_iow(DM9000_EPAR, offset);
 	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
 	DM9000_iow(DM9000_EPDRL, (val & 0xff));
 	DM9000_iow(DM9000_EPCR, 0x12);
 	udelay(8000);
 	DM9000_iow(DM9000_EPCR, 0);
 }
 /*
   Read a byte from I/O port
 */
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@ -28,6 +28,11 @@
 #define	PCIAUTO_IDE_MODE_MASK		0x05
 /* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
 #ifndef CFG_PCI_CACHE_LINE_SIZE
 #define CFG_PCI_CACHE_LINE_SIZE	8
 #endif
 /*
 *
 */
@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose,
 	}
 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
-	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 		CFG_PCI_CACHE_LINE_SIZE);
 	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 }
--- a/drivers/sil680.c
+++ b/drivers/sil680.c
@ -0,0 +1,110 @@
 /*
 * (C) Copyright 2007
 * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */
 /* sil680.c - ide support functions for the Sil0680A controller */
 /*
 * The following parameters must be defined in the configuration file
 * of the target board:
 *
 * #define CFG_IDE_SIL680
 *
 * #define CONFIG_PCI_PNP
 * NOTE it may also be necessary to define this if the default of 8 is
 * incorrect for the target board (e.g. the sequoia board requires 0).
 * #define CFG_PCI_CACHE_LINE_SIZE	0
 *
 * #define CONFIG_CMD_IDE
 * #undef  CONFIG_IDE_8xx_DIRECT
 * #undef  CONFIG_IDE_LED
 * #undef  CONFIG_IDE_RESET
 * #define CONFIG_IDE_PREINIT
 * #define CFG_IDE_MAXBUS		2 - modify to suit
 * #define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) - modify to suit
 * #define CFG_ATA_BASE_ADDR	0
 * #define CFG_ATA_IDE0_OFFSET	0
 * #define CFG_ATA_IDE1_OFFSET	0
 * #define CFG_ATA_DATA_OFFSET	0
 * #define CFG_ATA_REG_OFFSET	0
 * #define CFG_ATA_ALT_OFFSET	0x0004
 *
 * The mapping for PCI IO-space.
 * NOTE this is the value for the sequoia board. Modify to suit.
 * #define CFG_PCI0_IO_SPACE   0xE8000000
 */
 #include <common.h>
 #if defined(CFG_IDE_SIL680)
 #include <ata.h>
 #include <ide.h>
 #include <pci.h>
 extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
 int ide_preinit (void)
 {
 	int status;
 	pci_dev_t devbusfn;
 	int l;
 	status = 1;
 	for (l = 0; l < CFG_IDE_MAXBUS; l++) {
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
 	devbusfn = pci_find_device (0x1095, 0x0680, 0);
 	if (devbusfn != -1) {
 		status = 0;
 		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
 				       (u32 *) &ide_bus_offset[0]);
 		ide_bus_offset[0] &= 0xfffffff8;
 		ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
 		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
 				       (u32 *) &ide_bus_offset[1]);
 		ide_bus_offset[1] &= 0xfffffff8;
 		ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
 		/* init various things - taken from the Linux driver */
 		/* set PIO mode */
 		pci_write_config_byte(devbusfn, 0x80, 0x00);
 		pci_write_config_byte(devbusfn, 0x84, 0x00);
 		/* IDE0 */
 		pci_write_config_byte(devbusfn,  0xA1, 0x02);
 		pci_write_config_word(devbusfn,  0xA2, 0x328A);
 		pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
 		pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
 		pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
 		/* IDE1 */
 		pci_write_config_byte(devbusfn,  0xB1, 0x02);
 		pci_write_config_word(devbusfn,  0xB2, 0x328A);
 		pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
 		pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
 		pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
 	}
 	return (status);
 }
 void ide_set_reset (int flag) {
 	return;
 }
 #endif /* CFG_IDE_SIL680 */
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@ -1288,15 +1288,15 @@ typedef void		(*ExcpHndlr) (void) ;
 #define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
 #define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)
-#define GPLR(x)		((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
+#define GPLR(x)		__REG2(0x40E00000 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GPDR(x)		((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
+#define GPDR(x)		__REG2(0x40E0000C + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GPSR(x)		((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
+#define GPSR(x)		__REG2(0x40E00018 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GPCR(x)		((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
+#define GPCR(x)		__REG2(0x40E00024 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GRER(x)		((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
+#define GRER(x)		__REG2(0x40E00030 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GFER(x)		((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
+#define GFER(x)		__REG2(0x40E0003C + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GEDR(x)		((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
+#define GEDR(x)		__REG2(0x40E00048 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
-#define GAFR(x)		((((x) & 0x7f) < 96) ? _GAFR(x) : \
+#define GAFR(x)		__REG2((((x) & 0x7f) < 96) ?  0x40E00054 : \
-			 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+			 ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
 #else
 #define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@ -1,126 +1,31 @@
-/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
+/*
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
 * Copyright (c) 2000 by Silicon Graphics, Inc.
 * Copyright (c) 2001 MIPS Technologies, Inc.
 */
-#ifndef __ASM_MIPS_STRING_H
+#ifndef _ASM_STRING_H
-#define __ASM_MIPS_STRING_H
+#define _ASM_STRING_H
-#include <linux/config.h>
+/*
 * We don't do inline string functions, since the
 * optimised inline asm versions are not small.
 */
-#define __HAVE_ARCH_STRCPY
+#undef __HAVE_ARCH_STRCPY
-extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
+extern char *strcpy(char *__dest, __const__ char *__src);
 {
  char *__xdest = __dest;
-  __asm__ __volatile__(
+#undef __HAVE_ARCH_STRNCPY
-	".set\tnoreorder\n\t"
+extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
 	".set\tnoat\n"
 	"1:\tlbu\t$1,(%1)\n\t"
 	"addiu\t%1,1\n\t"
 	"sb\t$1,(%0)\n\t"
 	"bnez\t$1,1b\n\t"
 	"addiu\t%0,1\n\t"
 	".set\tat\n\t"
 	".set\treorder"
 	: "=r" (__dest), "=r" (__src)
 	: "0" (__dest), "1" (__src)
 	: "$1","memory");
-  return __xdest;
+#undef __HAVE_ARCH_STRCMP
-}
+extern int strcmp(__const__ char *__cs, __const__ char *__ct);
-#define __HAVE_ARCH_STRNCPY
+#undef __HAVE_ARCH_STRNCMP
-extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
 {
  char *__xdest = __dest;
  if (__n == 0)
    return __xdest;
  __asm__ __volatile__(
 	".set\tnoreorder\n\t"
 	".set\tnoat\n"
 	"1:\tlbu\t$1,(%1)\n\t"
 	"subu\t%2,1\n\t"
 	"sb\t$1,(%0)\n\t"
 	"beqz\t$1,2f\n\t"
 	"addiu\t%0,1\n\t"
 	"bnez\t%2,1b\n\t"
 	"addiu\t%1,1\n"
 	"2:\n\t"
 	".set\tat\n\t"
 	".set\treorder"
 	: "=r" (__dest), "=r" (__src), "=r" (__n)
 	: "0" (__dest), "1" (__src), "2" (__n)
 	: "$1","memory");
  return __dest;
 }
 #define __HAVE_ARCH_STRCMP
 extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
 {
  int __res;
  __asm__ __volatile__(
 	".set\tnoreorder\n\t"
 	".set\tnoat\n\t"
 	"lbu\t%2,(%0)\n"
 	"1:\tlbu\t$1,(%1)\n\t"
 	"addiu\t%0,1\n\t"
 	"bne\t$1,%2,2f\n\t"
 	"addiu\t%1,1\n\t"
 	"bnez\t%2,1b\n\t"
 	"lbu\t%2,(%0)\n\t"
 #if defined(CONFIG_CPU_R3000)
 	"nop\n\t"
 #endif
 	"move\t%2,$1\n"
 	"2:\tsubu\t%2,$1\n"
 	"3:\t.set\tat\n\t"
 	".set\treorder"
 	: "=r" (__cs), "=r" (__ct), "=r" (__res)
 	: "0" (__cs), "1" (__ct)
 	: "$1");
  return __res;
 }
 #define __HAVE_ARCH_STRNCMP
 extern __inline__ int
 strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
 {
 	int __res;
 	__asm__ __volatile__(
 	".set\tnoreorder\n\t"
 	".set\tnoat\n"
 	"1:\tlbu\t%3,(%0)\n\t"
 	"beqz\t%2,2f\n\t"
 	"lbu\t$1,(%1)\n\t"
 	"subu\t%2,1\n\t"
 	"bne\t$1,%3,3f\n\t"
 	"addiu\t%0,1\n\t"
 	"bnez\t%3,1b\n\t"
 	"addiu\t%1,1\n"
 	"2:\n\t"
 #if defined(CONFIG_CPU_R3000)
 	"nop\n\t"
 #endif
 	"move\t%3,$1\n"
 	"3:\tsubu\t%3,$1\n\t"
 	".set\tat\n\t"
 	".set\treorder"
 	: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
 	: "0" (__cs), "1" (__ct), "2" (__count)
 	: "$1");
 	return __res;
 }
 #undef __HAVE_ARCH_MEMSET
 extern void *memset(void *__s, int __c, size_t __count);
@ -131,27 +36,4 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
 #undef __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-/* Don't build bcopy at all ...  */
+#endif /* _ASM_STRING_H */
 #define __HAVE_ARCH_BCOPY
 #define __HAVE_ARCH_MEMSCAN
 extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
 {
 	char *__end = (char *)__addr + __size;
 	__asm__(".set\tpush\n\t"
 		".set\tnoat\n\t"
 		".set\treorder\n\t"
 		"1:\tbeq\t%0,%1,2f\n\t"
 		"addiu\t%0,1\n\t"
 		"lb\t$1,-1(%0)\n\t"
 		"bne\t$1,%4,1b\n"
 		"2:\t.set\tpop"
 		: "=r" (__addr), "=r" (__end)
 		: "0" (__addr), "1" (__end), "r" (__c)
 		: "$1");
 	return __addr;
 }
 #endif /* __ASM_MIPS_STRING_H */
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@ -178,7 +178,7 @@
 #endif /* CONFIG_MPC5200 */
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define OF_CPU			"PowerPC,5200@0"
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@ -310,6 +310,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE3_IO_BASE	0x00000000
 #define CFG_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
 #define CFG_PCIE3_IO_SIZE	0x00100000	/* 1M */
 #define CFG_PCIE3_MEM_BASE2	0xb0200000
 #define CFG_PCIE3_MEM_PHYS2	CFG_PCIE3_MEM_BASE2
 #define CFG_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
 #if defined(CONFIG_PCI)
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@ -701,7 +701,7 @@
 * Open firmware flat tree support
 *-----------------------------------------------------------------------
 */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define OF_CPU			"PowerPC,5200@0"
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@ -145,7 +145,7 @@
 #if 0
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define OF_CPU			"PowerPC,5200@0"
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@ -417,7 +417,7 @@ extern void __led_set(led_id_t id, int state);
 #define CFG_RESET_ADDRESS	0xfff00100
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 #define OF_CPU			"PowerPC,5200@0"
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@ -400,7 +400,8 @@
 *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI			/* include pci support	        */
-#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
 #define CFG_PCI_CACHE_LINE_SIZE	0 /* to avoid problems with PNP */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@ -0,0 +1,325 @@
 /*
 * (C) Copyright 2007
 * Stefano Babic, DENX Gmbh, sbabic@denx.de
 *
 * (C) Copyright 2004
 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
 *
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the LUBBOCK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
 * High Level Configuration Options
 * (easy to change)
 */
 #define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
 #define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
 #define CONFIG_MMC		1
 #define BOARD_LATE_INIT		1
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 #define RTC
 /*
 * Size of malloc() pool
 */
 #define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
 #define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 /*
 * Hardware drivers
 */
 /*
 * select serial console configuration
 */
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_FFUART	       1       /* we use FFUART on Conxs */
 #define CONFIG_BTUART	       1       /* we use BTUART on Conxs */
 #define CONFIG_STUART	       1       /* we use STUART on Conxs */
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE	       38400
 #define CONFIG_DOS_PARTITION   1
 /*
 * Command line configuration.
 */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_IMLS
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_USB
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_SERVERIP		192.168.1.99
 #define CONFIG_BOOTCOMMAND	"run boot_flash"
 #define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
 				" rw root=/dev/ram initrd=0xa0800000,5m"
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"program_boot_mmc="						\
 			"mw.b 0xa0010000 0xff 0x20000; "		\
 			"if	 mmcinit && "				\
 				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
 			"then "						\
 				"protect off 0x0 0x1ffff; "		\
 				"erase 0x0 0x1ffff; "			\
 				"cp.b 0xa0010000 0x0 0x20000; "		\
 			"fi\0"						\
 	"program_uzImage_mmc="						\
 			"mw.b 0xa0010000 0xff 0x180000; "		\
 			"if	 mmcinit && "				\
 				"fatload mmc 0 0xa0010000 uzImage; "	\
 			"then "						\
 				"protect off 0x40000 0x1bffff; "	\
 				"erase 0x40000 0x1bffff; "		\
 				"cp.b 0xa0010000 0x40000 0x180000; "	\
 			"fi\0"						\
 	"program_ramdisk_mmc="						\
 			"mw.b 0xa0010000 0xff 0x500000; "		\
 			"if	 mmcinit && "				\
 				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
 			"then "						\
 				"protect off 0x1c0000 0x6bffff; "	\
 				"erase 0x1c0000 0x6bffff; "		\
 				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
 			"fi\0"						\
 	"boot_mmc="							\
 			"if	 mmcinit && "				\
 				"fatload mmc 0 0xa0030000 uzImage && "	\
 				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
 			"then "						\
 				"bootm 0xa0030000; "			\
 			"fi\0"						\
 	"boot_flash="							\
 			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
 			"bootm 0x40000\0"				\
 #define CONFIG_SETUP_MEMORY_TAGS 1
 #define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
 /* #define CONFIG_INITRD_TAG	 1 */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
 #endif
 /*
 * Miscellaneous configurable options
 */
 #define CFG_HUSH_PARSER		1
 #define CFG_PROMPT_HUSH_PS2	"> "
 #define CFG_LONGHELP				/* undef to save memory		*/
 #ifdef CFG_HUSH_PARSER
 #define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
 #else
 #define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
 #endif
 #define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS		16		/* max number of command args	*/
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_DEVICE_NULLDEV	1
 #define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 #undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 #define CFG_LOAD_ADDR		0xa1000000	/* default load address */
 #define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
 #define CFG_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 						/* valid baudrates */
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #define CFG_MMC_BASE		0xF0000000
 /*
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
 #define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 #ifdef CONFIG_USE_IRQ
 #define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
 #define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
 #endif
 /*
 * Physical Memory Map
 */
 #define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
 #define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
 #define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
 #define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
 #define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
 #define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
 #define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define CFG_DRAM_BASE		0xa0000000
 #define CFG_DRAM_SIZE		0x04000000
 #define CFG_FLASH_BASE		PHYS_FLASH_1
 /*
 * GPIO settings
 */
 #define CFG_GPSR0_VAL		0x00018000
 #define CFG_GPSR1_VAL		0x00000000
 #define CFG_GPSR2_VAL		0x400dc000
 #define CFG_GPSR3_VAL		0x00000000
 #define CFG_GPCR0_VAL		0x00000000
 #define CFG_GPCR1_VAL		0x00000000
 #define CFG_GPCR2_VAL		0x00000000
 #define CFG_GPCR3_VAL		0x00000000
 #define CFG_GPDR0_VAL		0x00018000
 #define CFG_GPDR1_VAL		0x00028801
 #define CFG_GPDR2_VAL		0x520dc000
 #define CFG_GPDR3_VAL		0x0001E000
 #define CFG_GAFR0_L_VAL		0x801c0000
 #define CFG_GAFR0_U_VAL		0x00000013
 #define CFG_GAFR1_L_VAL		0x6990100A
 #define CFG_GAFR1_U_VAL		0x00000008
 #define CFG_GAFR2_L_VAL		0xA0000000
 #define CFG_GAFR2_U_VAL		0x010900F2
 #define CFG_GAFR3_L_VAL		0x54000003
 #define CFG_GAFR3_U_VAL		0x00002401
 #define CFG_GRER0_VAL		0x00000000
 #define CFG_GRER1_VAL		0x00000000
 #define CFG_GRER2_VAL		0x00000000
 #define CFG_GRER3_VAL		0x00000000
 #define CFG_GFER0_VAL		0x00000000
 #define CFG_GFER1_VAL		0x00000000
 #define CFG_GFER2_VAL		0x00000000
 #define CFG_GFER3_VAL		0x00000020
 #define CFG_PSSR_VAL		0x20	/* CHECK */
 /*
 * Clock settings
 */
 #define CFG_CKEN		0x01FFFFFF	/* CHECK */
 #define CFG_CCCR		0x02000290 /*   520Mhz */
 /*
 * Memory settings
 */
 #define CFG_MSC0_VAL		0x4df84df0
 #define CFG_MSC1_VAL		0x7ff87ff4
 #define CFG_MSC2_VAL		0xa26936d4
 #define CFG_MDCNFG_VAL		0x880009C9
 #define CFG_MDREFR_VAL		0x20ca201e
 #define CFG_MDMRS_VAL		0x00220022
 #define CFG_FLYCNFG_VAL		0x00000000
 #define CFG_SXCNFG_VAL		0x40044004
 /*
 * PCMCIA and CF Interfaces
 */
 #define CFG_MECR_VAL		0x00000001
 #define CFG_MCMEM0_VAL		0x00004204
 #define CFG_MCMEM1_VAL		0x00010204
 #define CFG_MCATT0_VAL		0x00010504
 #define CFG_MCATT1_VAL		0x00010504
 #define CFG_MCIO0_VAL		0x00008407
 #define CFG_MCIO1_VAL		0x0000c108
 #define CONFIG_DRIVER_DM9000		1
 #define CONFIG_DRIVER_DM9000		1
 #define CONFIG_DM9000_BASE	0x08000000
 #define DM9000_IO			CONFIG_DM9000_BASE
 #define DM9000_DATA			(CONFIG_DM9000_BASE+0x8004)
 /* #define CONFIG_DM9000_USE_8BIT */
 /* #define CONFIG_DM9000_USE_16BIT */
 #define CONFIG_DM9000_USE_32BIT
 #define CONFIG_USB_OHCI_NEW	1
 #define CFG_USB_OHCI_BOARD_INIT	1
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	3
 #define CFG_USB_OHCI_REGS_BASE	0x4C000000
 #define CFG_USB_OHCI_SLOT_NAME	"trizepsiv"
 #define CONFIG_USB_STORAGE	1
 #define CFG_USB_OHCI_CPU_INIT	1
 /*
 * FLASH and environment organization
 */
 #define CFG_FLASH_CFI
 #define CFG_FLASH_CFI_DRIVER	1
 #define CFG_MONITOR_BASE	0
 #define CFG_MONITOR_LEN		0x40000
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
 #define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip    */
 /* timeout values are in ticks */
 #define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
 #define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
 /* write flash less slowly */
 #define CFG_FLASH_USE_BUFFER_WRITE 1
 /* Flash environment locations */
 #define CFG_ENV_IS_IN_FLASH	1
 #define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
 #define CFG_ENV_SIZE		0x40000	/* Total Size of Environment     	*/
 #define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
 #endif	/* __CONFIG_H */
--- a/include/libfdt.h
+++ b/include/libfdt.h
@ -140,6 +140,8 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
 	})
 #define fdt_setprop_string(fdt, nodeoffset, name, str) \
 	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
 int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
 			 const void *val, int len, int create);
 int fdt_delprop(void *fdt, int nodeoffset, const char *name);
 int fdt_add_subnode_namelen(void *fdt, int parentoffset,
 			    const char *name, int namelen);
--- a/include/serial.h
+++ b/include/serial.h
@ -36,6 +36,10 @@ extern struct serial_device eserial4_device;
 #endif
 extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
 extern void serial_initialize(void);
 extern void serial_devices_init(void);
 extern int serial_assign(char * name);
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@ -338,6 +338,10 @@ void start_armboot (void)
 	drv_vfd_init();
 #endif /* CONFIG_VFD */
 #ifdef CONFIG_SERIAL_MULTI
 	serial_initialize();
 #endif
 	/* IP Address */
 	gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
--- a/libfdt/fdt_rw.c
+++ b/libfdt/fdt_rw.c
@ -188,6 +188,32 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name,
 	return 0;
 }
 /**
 * fdt_find_and_setprop: Find a node and set it's property
 *
 * @fdt: ptr to device tree
 * @node: path of node
 * @prop: property name
 * @val: ptr to new value
 * @len: length of new property value
 * @create: flag to create the property if it doesn't exist
 *
 * Convenience function to directly set a property given the path to the node.
 */
 int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
 			 const void *val, int len, int create)
 {
 	int nodeoff = fdt_find_node_by_path(fdt, node);
 	if (nodeoff < 0)
 		return nodeoff;
 	if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL))
 		return 0; /* create flag not set; so exit quietly */
 	return fdt_setprop(fdt, nodeoff, prop, val, len);
 }
 int fdt_delprop(void *fdt, int nodeoffset, const char *name)
 {
 	struct fdt_property *prop;