mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-11 05:02:26 -04:00
Code cleanup
This commit is contained in:
Wolfgang Denk
parent
034df411c1
commit
47a6989c10
@ -40,8 +40,8 @@
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#include <asm/cache.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#define CONFIG_IDENT_STRING ""
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#endif
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#endif
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/* We don't want the MMU yet.
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/* We don't want the MMU yet.
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@ -188,11 +188,11 @@ boot_warm:
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#if (CONFIG_NUM_CPUS > 1)
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#if (CONFIG_NUM_CPUS > 1)
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mfspr r0, MSSCR0
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mfspr r0, MSSCR0
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andi. r0, r0, 0x0020
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andi. r0, r0, 0x0020
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rlwinm r0,r0,27,31,31
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rlwinm r0,r0,27,31,31
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mtspr PIR, r0
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mtspr PIR, r0
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beq 1f
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beq 1f
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bl secondary_cpu_setup
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bl secondary_cpu_setup
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#endif
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#endif
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/* disable everything */
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/* disable everything */
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@ -249,7 +249,7 @@ in_flash:
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stw r4, 0(r3)
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stw r4, 0(r3)
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/* setup the law entries */
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/* setup the law entries */
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bl law_entry
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bl law_entry
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sync
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sync
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/* Don't use this feature due to bug in 8641D PD4 */
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/* Don't use this feature due to bug in 8641D PD4 */
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@ -303,7 +303,7 @@ in_flash:
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/* enable and invalidate the data cache */
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/* enable and invalidate the data cache */
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/* bl l1dcache_enable */
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/* bl l1dcache_enable */
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bl dcache_enable
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bl dcache_enable
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sync
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sync
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#if 1
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#if 1
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@ -320,56 +320,56 @@ in_flash:
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lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
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ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
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li r0, 0 /* Make room for stack frame header and */
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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GET_GOT /* initialize GOT access */
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GET_GOT /* initialize GOT access */
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/* run low-level CPU init code (from Flash) */
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/* run low-level CPU init code (from Flash) */
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bl cpu_init_f
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bl cpu_init_f
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sync
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sync
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#ifdef RUN_DIAG
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#ifdef RUN_DIAG
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/* Sri: Code to run the diagnostic automatically */
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/* Sri: Code to run the diagnostic automatically */
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/* Load PX_AUX register address in r4 */
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/* Load PX_AUX register address in r4 */
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lis r4, 0xf810
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lis r4, 0xf810
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ori r4, r4, 0x6
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ori r4, r4, 0x6
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/* Load contents of PX_AUX in r3 bits 24 to 31*/
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/* Load contents of PX_AUX in r3 bits 24 to 31*/
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lbz r3, 0(r4)
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lbz r3, 0(r4)
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/* Mask and obtain the bit in r3 */
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/* Mask and obtain the bit in r3 */
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rlwinm. r3, r3, 0, 24, 24
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rlwinm. r3, r3, 0, 24, 24
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/* If not zero, jump and continue with u-boot */
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/* If not zero, jump and continue with u-boot */
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bne diag_done
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bne diag_done
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/* Load back contents of PX_AUX in r3 bits 24 to 31 */
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/* Load back contents of PX_AUX in r3 bits 24 to 31 */
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lbz r3, 0(r4)
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lbz r3, 0(r4)
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/* Set the MSB of the register value */
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/* Set the MSB of the register value */
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ori r3, r3, 0x80
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ori r3, r3, 0x80
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/* Write value in r3 back to PX_AUX */
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/* Write value in r3 back to PX_AUX */
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stb r3, 0(r4)
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stb r3, 0(r4)
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/* Get the address to jump to in r3*/
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/* Get the address to jump to in r3*/
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lis r3, CFG_DIAG_ADDR@h
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lis r3, CFG_DIAG_ADDR@h
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ori r3, r3, CFG_DIAG_ADDR@l
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ori r3, r3, CFG_DIAG_ADDR@l
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/* Load the LR with the branch address */
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/* Load the LR with the branch address */
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mtlr r3
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mtlr r3
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/* Branch to diagnostic */
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/* Branch to diagnostic */
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blr
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blr
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diag_done:
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diag_done:
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#endif
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#endif
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/* bl l2cache_enable*/
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/* bl l2cache_enable */
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mr r3, r21
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mr r3, r21
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/* r3: BOOTFLAG */
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/* r3: BOOTFLAG */
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/* run 1st part of board init code (from Flash) */
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/* run 1st part of board init code (from Flash) */
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bl board_init_f
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bl board_init_f
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sync
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sync
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@ -383,20 +383,20 @@ invalidate_bats:
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mtspr IBAT1U, r0
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mtspr IBAT1U, r0
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mtspr IBAT2U, r0
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mtspr IBAT2U, r0
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mtspr IBAT3U, r0
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mtspr IBAT3U, r0
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mtspr IBAT4U, r0
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mtspr IBAT4U, r0
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mtspr IBAT5U, r0
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mtspr IBAT5U, r0
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mtspr IBAT6U, r0
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mtspr IBAT6U, r0
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mtspr IBAT7U, r0
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mtspr IBAT7U, r0
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isync
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isync
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mtspr DBAT0U, r0
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mtspr DBAT0U, r0
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mtspr DBAT1U, r0
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mtspr DBAT1U, r0
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mtspr DBAT2U, r0
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mtspr DBAT2U, r0
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mtspr DBAT3U, r0
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mtspr DBAT3U, r0
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mtspr DBAT4U, r0
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mtspr DBAT4U, r0
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mtspr DBAT5U, r0
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mtspr DBAT5U, r0
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mtspr DBAT6U, r0
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mtspr DBAT6U, r0
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mtspr DBAT7U, r0
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mtspr DBAT7U, r0
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isync
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isync
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sync
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sync
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@ -482,80 +482,80 @@ setup_bats:
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isync
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isync
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/* IBAT 4 */
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/* IBAT 4 */
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addis r4, r0, CFG_IBAT4L@h
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addis r4, r0, CFG_IBAT4L@h
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ori r4, r4, CFG_IBAT4L@l
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ori r4, r4, CFG_IBAT4L@l
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addis r3, r0, CFG_IBAT4U@h
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addis r3, r0, CFG_IBAT4U@h
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ori r3, r3, CFG_IBAT4U@l
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ori r3, r3, CFG_IBAT4U@l
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mtspr IBAT4L, r4
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mtspr IBAT4L, r4
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mtspr IBAT4U, r3
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mtspr IBAT4U, r3
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isync
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isync
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/* DBAT 4 */
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/* DBAT 4 */
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addis r4, r0, CFG_DBAT4L@h
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addis r4, r0, CFG_DBAT4L@h
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ori r4, r4, CFG_DBAT4L@l
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ori r4, r4, CFG_DBAT4L@l
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addis r3, r0, CFG_DBAT4U@h
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addis r3, r0, CFG_DBAT4U@h
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ori r3, r3, CFG_DBAT4U@l
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ori r3, r3, CFG_DBAT4U@l
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mtspr DBAT4L, r4
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mtspr DBAT4L, r4
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mtspr DBAT4U, r3
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mtspr DBAT4U, r3
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isync
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isync
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/* IBAT 5 */
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/* IBAT 5 */
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addis r4, r0, CFG_IBAT5L@h
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addis r4, r0, CFG_IBAT5L@h
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ori r4, r4, CFG_IBAT5L@l
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ori r4, r4, CFG_IBAT5L@l
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addis r3, r0, CFG_IBAT5U@h
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addis r3, r0, CFG_IBAT5U@h
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ori r3, r3, CFG_IBAT5U@l
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ori r3, r3, CFG_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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mtspr IBAT5U, r3
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isync
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isync
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/* DBAT 5 */
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/* DBAT 5 */
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addis r4, r0, CFG_DBAT5L@h
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addis r4, r0, CFG_DBAT5L@h
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ori r4, r4, CFG_DBAT5L@l
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ori r4, r4, CFG_DBAT5L@l
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addis r3, r0, CFG_DBAT5U@h
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addis r3, r0, CFG_DBAT5U@h
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ori r3, r3, CFG_DBAT5U@l
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ori r3, r3, CFG_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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mtspr DBAT5U, r3
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isync
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isync
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/* IBAT 6 */
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/* IBAT 6 */
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addis r4, r0, CFG_IBAT6L@h
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addis r4, r0, CFG_IBAT6L@h
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ori r4, r4, CFG_IBAT6L@l
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ori r4, r4, CFG_IBAT6L@l
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addis r3, r0, CFG_IBAT6U@h
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addis r3, r0, CFG_IBAT6U@h
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ori r3, r3, CFG_IBAT6U@l
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ori r3, r3, CFG_IBAT6U@l
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mtspr IBAT6L, r4
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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mtspr IBAT6U, r3
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isync
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isync
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/* DBAT 6 */
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/* DBAT 6 */
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addis r4, r0, CFG_DBAT6L@h
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addis r4, r0, CFG_DBAT6L@h
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ori r4, r4, CFG_DBAT6L@l
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ori r4, r4, CFG_DBAT6L@l
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addis r3, r0, CFG_DBAT6U@h
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addis r3, r0, CFG_DBAT6U@h
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ori r3, r3, CFG_DBAT6U@l
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ori r3, r3, CFG_DBAT6U@l
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mtspr DBAT6L, r4
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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mtspr DBAT6U, r3
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isync
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isync
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/* IBAT 7 */
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/* IBAT 7 */
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addis r4, r0, CFG_IBAT7L@h
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addis r4, r0, CFG_IBAT7L@h
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ori r4, r4, CFG_IBAT7L@l
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ori r4, r4, CFG_IBAT7L@l
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addis r3, r0, CFG_IBAT7U@h
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addis r3, r0, CFG_IBAT7U@h
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ori r3, r3, CFG_IBAT7U@l
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ori r3, r3, CFG_IBAT7U@l
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mtspr IBAT7L, r4
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mtspr IBAT7L, r4
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mtspr IBAT7U, r3
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mtspr IBAT7U, r3
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isync
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isync
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/* DBAT 7 */
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/* DBAT 7 */
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addis r4, r0, CFG_DBAT7L@h
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addis r4, r0, CFG_DBAT7L@h
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ori r4, r4, CFG_DBAT7L@l
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ori r4, r4, CFG_DBAT7L@l
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addis r3, r0, CFG_DBAT7U@h
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addis r3, r0, CFG_DBAT7U@h
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ori r3, r3, CFG_DBAT7U@l
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ori r3, r3, CFG_DBAT7U@l
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mtspr DBAT7L, r4
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mtspr DBAT7L, r4
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mtspr DBAT7U, r3
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mtspr DBAT7U, r3
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isync
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isync
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1:
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1:
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addis r3, 0, 0x0000
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addis r3, 0, 0x0000
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addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
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addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
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isync
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isync
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tlblp:
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tlblp:
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@ -663,8 +663,8 @@ get_svr:
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/*
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/*
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* Function: in8
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* Function: in8
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* Description: Input 8 bits
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* Description: Input 8 bits
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*/
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*/
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.globl in8
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.globl in8
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in8:
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in8:
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@ -672,8 +672,8 @@ in8:
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blr
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blr
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/*
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/*
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* Function: out8
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* Function: out8
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* Description: Output 8 bits
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* Description: Output 8 bits
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*/
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*/
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.globl out8
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.globl out8
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out8:
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out8:
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@ -681,8 +681,8 @@ out8:
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blr
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blr
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/*
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/*
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* Function: out16
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* Function: out16
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* Description: Output 16 bits
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* Description: Output 16 bits
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*/
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*/
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.globl out16
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.globl out16
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out16:
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out16:
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@ -690,8 +690,8 @@ out16:
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blr
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blr
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/*
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/*
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* Function: out16r
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* Function: out16r
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* Description: Byte reverse and output 16 bits
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* Description: Byte reverse and output 16 bits
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*/
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*/
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.globl out16r
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.globl out16r
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out16r:
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out16r:
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@ -699,8 +699,8 @@ out16r:
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blr
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blr
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/*
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/*
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* Function: out32
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* Function: out32
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* Description: Output 32 bits
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* Description: Output 32 bits
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*/
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*/
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.globl out32
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.globl out32
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out32:
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out32:
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@ -708,8 +708,8 @@ out32:
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blr
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blr
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/*
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/*
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* Function: out32r
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* Function: out32r
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* Description: Byte reverse and output 32 bits
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* Description: Byte reverse and output 32 bits
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*/
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*/
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.globl out32r
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.globl out32r
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out32r:
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out32r:
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@ -717,8 +717,8 @@ out32r:
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blr
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blr
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/*
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/*
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* Function: in16
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* Function: in16
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* Description: Input 16 bits
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* Description: Input 16 bits
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*/
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*/
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.globl in16
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.globl in16
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in16:
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in16:
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@ -726,8 +726,8 @@ in16:
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blr
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blr
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/*
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/*
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* Function: in16r
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* Function: in16r
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* Description: Input 16 bits and byte reverse
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* Description: Input 16 bits and byte reverse
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*/
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*/
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.globl in16r
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.globl in16r
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in16r:
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in16r:
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@ -735,8 +735,8 @@ in16r:
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blr
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blr
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/*
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/*
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* Function: in32
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* Function: in32
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* Description: Input 32 bits
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* Description: Input 32 bits
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*/
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*/
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.globl in32
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.globl in32
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in32:
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in32:
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@ -744,8 +744,8 @@ in32:
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blr
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blr
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/*
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/*
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* Function: in32r
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* Function: in32r
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* Description: Input 32 bits and byte reverse
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* Description: Input 32 bits and byte reverse
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*/
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*/
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.globl in32r
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.globl in32r
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in32r:
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in32r:
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@ -753,10 +753,10 @@ in32r:
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blr
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blr
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/*
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/*
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* Function: ppcDcbf
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* Function: ppcDcbf
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* Description: Data Cache block flush
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* Description: Data Cache block flush
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* Input: r3 = effective address
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* Input: r3 = effective address
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* Output: none.
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* Output: none.
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*/
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*/
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.globl ppcDcbf
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.globl ppcDcbf
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ppcDcbf:
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ppcDcbf:
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@ -764,10 +764,10 @@ ppcDcbf:
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blr
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blr
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|
|
||||||
/*
|
/*
|
||||||
* Function: ppcDcbi
|
* Function: ppcDcbi
|
||||||
* Description: Data Cache block Invalidate
|
* Description: Data Cache block Invalidate
|
||||||
* Input: r3 = effective address
|
* Input: r3 = effective address
|
||||||
* Output: none.
|
* Output: none.
|
||||||
*/
|
*/
|
||||||
.globl ppcDcbi
|
.globl ppcDcbi
|
||||||
ppcDcbi:
|
ppcDcbi:
|
||||||
@ -775,10 +775,10 @@ ppcDcbi:
|
|||||||
blr
|
blr
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Function: ppcDcbz
|
* Function: ppcDcbz
|
||||||
* Description: Data Cache block zero.
|
* Description: Data Cache block zero.
|
||||||
* Input: r3 = effective address
|
* Input: r3 = effective address
|
||||||
* Output: none.
|
* Output: none.
|
||||||
*/
|
*/
|
||||||
.globl ppcDcbz
|
.globl ppcDcbz
|
||||||
ppcDcbz:
|
ppcDcbz:
|
||||||
@ -786,10 +786,10 @@ ppcDcbz:
|
|||||||
blr
|
blr
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Function: ppcSync
|
* Function: ppcSync
|
||||||
* Description: Processor Synchronize
|
* Description: Processor Synchronize
|
||||||
* Input: none.
|
* Input: none.
|
||||||
* Output: none.
|
* Output: none.
|
||||||
*/
|
*/
|
||||||
.globl ppcSync
|
.globl ppcSync
|
||||||
ppcSync:
|
ppcSync:
|
||||||
@ -810,7 +810,7 @@ ppcSync:
|
|||||||
.globl relocate_code
|
.globl relocate_code
|
||||||
relocate_code:
|
relocate_code:
|
||||||
|
|
||||||
mr r1, r3 /* Set new stack pointer */
|
mr r1, r3 /* Set new stack pointer */
|
||||||
mr r9, r4 /* Save copy of Global Data pointer */
|
mr r9, r4 /* Save copy of Global Data pointer */
|
||||||
mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
|
mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */
|
||||||
mr r10, r5 /* Save copy of Destination Address */
|
mr r10, r5 /* Save copy of Destination Address */
|
||||||
@ -891,7 +891,7 @@ relocate_code:
|
|||||||
add r4,r4,r6
|
add r4,r4,r6
|
||||||
cmplw r4,r5
|
cmplw r4,r5
|
||||||
blt 6b
|
blt 6b
|
||||||
7: sync /* Wait for all icbi to complete on bus */
|
7: sync /* Wait for all icbi to complete on bus */
|
||||||
isync
|
isync
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -1051,9 +1051,9 @@ trap_reloc:
|
|||||||
.globl enable_ext_addr
|
.globl enable_ext_addr
|
||||||
enable_ext_addr:
|
enable_ext_addr:
|
||||||
mfspr r0, HID0
|
mfspr r0, HID0
|
||||||
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
|
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
|
||||||
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
|
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
|
||||||
mtspr HID0, r0
|
mtspr HID0, r0
|
||||||
sync
|
sync
|
||||||
isync
|
isync
|
||||||
blr
|
blr
|
||||||
@ -1065,8 +1065,8 @@ setup_ccsrbar:
|
|||||||
lis r4, CFG_CCSRBAR_DEFAULT@h
|
lis r4, CFG_CCSRBAR_DEFAULT@h
|
||||||
ori r4, r4, CFG_CCSRBAR_DEFAULT@l
|
ori r4, r4, CFG_CCSRBAR_DEFAULT@l
|
||||||
|
|
||||||
lis r5, CFG_CCSRBAR@h
|
lis r5, CFG_CCSRBAR@h
|
||||||
ori r5, r5, CFG_CCSRBAR@l
|
ori r5, r5, CFG_CCSRBAR@l
|
||||||
srwi r6,r5,12
|
srwi r6,r5,12
|
||||||
stw r6, 0(r4)
|
stw r6, 0(r4)
|
||||||
isync
|
isync
|
||||||
@ -1130,36 +1130,36 @@ unlock_ram_in_cache:
|
|||||||
1: icbi r0, r3
|
1: icbi r0, r3
|
||||||
addi r3, r3, 32
|
addi r3, r3, 32
|
||||||
bdnz 1b
|
bdnz 1b
|
||||||
sync /* Wait for all icbi to complete on bus */
|
sync /* Wait for all icbi to complete on bus */
|
||||||
isync
|
isync
|
||||||
#if 1
|
#if 1
|
||||||
/* Unlock the data cache and invalidate it */
|
/* Unlock the data cache and invalidate it */
|
||||||
mfspr r0, HID0
|
mfspr r0, HID0
|
||||||
li r3,0x1000
|
li r3,0x1000
|
||||||
andc r0,r0,r3
|
andc r0,r0,r3
|
||||||
li r3,0x0400
|
li r3,0x0400
|
||||||
or r0,r0,r3
|
or r0,r0,r3
|
||||||
sync
|
sync
|
||||||
mtspr HID0, r0
|
mtspr HID0, r0
|
||||||
sync
|
sync
|
||||||
blr
|
blr
|
||||||
#endif
|
#endif
|
||||||
#if 0
|
#if 0
|
||||||
/* Unlock the first way of the data cache */
|
/* Unlock the first way of the data cache */
|
||||||
mfspr r0, LDSTCR
|
mfspr r0, LDSTCR
|
||||||
li r3,0x0080
|
li r3,0x0080
|
||||||
andc r0,r0,r3
|
andc r0,r0,r3
|
||||||
#ifdef CONFIG_ALTIVEC
|
#ifdef CONFIG_ALTIVEC
|
||||||
dssall
|
dssall
|
||||||
#endif
|
#endif
|
||||||
sync
|
sync
|
||||||
mtspr LDSTCR, r0
|
mtspr LDSTCR, r0
|
||||||
sync
|
sync
|
||||||
isync
|
isync
|
||||||
li r3,0x0400
|
li r3,0x0400
|
||||||
or r0,r0,r3
|
or r0,r0,r3
|
||||||
sync
|
sync
|
||||||
mtspr HID0, r0
|
mtspr HID0, r0
|
||||||
sync
|
sync
|
||||||
blr
|
blr
|
||||||
#endif
|
#endif
|
||||||
@ -1168,9 +1168,9 @@ unlock_ram_in_cache:
|
|||||||
/* If this is a multi-cpu system then we need to handle the
|
/* If this is a multi-cpu system then we need to handle the
|
||||||
* 2nd cpu. The assumption is that the 2nd cpu is being
|
* 2nd cpu. The assumption is that the 2nd cpu is being
|
||||||
* held in boot holdoff mode until the 1st cpu unlocks it
|
* held in boot holdoff mode until the 1st cpu unlocks it
|
||||||
* from Linux. We'll do some basic cpu init and then pass
|
* from Linux. We'll do some basic cpu init and then pass
|
||||||
* it to the Linux Reset Vector.
|
* it to the Linux Reset Vector.
|
||||||
* Sri: Much of this initialization is not required. Linux
|
* Sri: Much of this initialization is not required. Linux
|
||||||
* rewrites the bats, and the sprs and also enables the L1 cache.
|
* rewrites the bats, and the sprs and also enables the L1 cache.
|
||||||
*/
|
*/
|
||||||
#if (CONFIG_NUM_CPUS > 1)
|
#if (CONFIG_NUM_CPUS > 1)
|
||||||
@ -1199,27 +1199,27 @@ secondary_cpu_setup:
|
|||||||
bl dcache_enable
|
bl dcache_enable
|
||||||
sync
|
sync
|
||||||
|
|
||||||
/* enable and invalidate the instruction cache*/
|
/* enable and invalidate the instruction cache*/
|
||||||
bl icache_enable
|
bl icache_enable
|
||||||
sync
|
sync
|
||||||
|
|
||||||
/* TBEN in HID0 */
|
/* TBEN in HID0 */
|
||||||
mfspr r4, HID0
|
mfspr r4, HID0
|
||||||
oris r4, r4, 0x0400
|
oris r4, r4, 0x0400
|
||||||
mtspr HID0, r4
|
mtspr HID0, r4
|
||||||
sync
|
sync
|
||||||
isync
|
isync
|
||||||
|
|
||||||
/*SYNCBE|ABE in HID1*/
|
/*SYNCBE|ABE in HID1*/
|
||||||
mfspr r4, HID1
|
mfspr r4, HID1
|
||||||
ori r4, r4, 0x0C00
|
ori r4, r4, 0x0C00
|
||||||
mtspr HID1, r4
|
mtspr HID1, r4
|
||||||
sync
|
sync
|
||||||
isync
|
isync
|
||||||
|
|
||||||
lis r3, CONFIG_LINUX_RESET_VEC@h
|
lis r3, CONFIG_LINUX_RESET_VEC@h
|
||||||
ori r3, r3, CONFIG_LINUX_RESET_VEC@l
|
ori r3, r3, CONFIG_LINUX_RESET_VEC@l
|
||||||
mtlr r3
|
mtlr r3
|
||||||
blr
|
blr
|
||||||
|
|
||||||
/* Never Returns, Running in Linux Now */
|
/* Never Returns, Running in Linux Now */
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user