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OMAP3: fix DRAM size for IGEP-based boards.

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The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
This commit is contained in:
Enric Balletbò i Serra 2012-08-05 00:55:56 +00:00 committed by Albert ARIBAUD
parent be7d257895
commit 4833b0939a
2 changed files with 6 additions and 6 deletions
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6
board/isee/igep0020/igep0020.c
View File

@ -77,19 +77,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
{ {
*mr = MICRON_V_MR_165; *mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_200(512 << 20); *mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; *ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; *ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else #else
if (get_cpu_family() == CPU_OMAP34XX) { if (get_cpu_family() == CPU_OMAP34XX) {
*mcfg = NUMONYX_V_MCFG_165(512 << 20); *mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; *ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; *ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else { } else {
*mcfg = NUMONYX_V_MCFG_200(512 << 20); *mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200; *ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200; *ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;

6
board/isee/igep0030/igep0030.c
View File

@ -64,19 +64,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
{ {
*mr = MICRON_V_MR_165; *mr = MICRON_V_MR_165;
#ifdef CONFIG_BOOT_NAND #ifdef CONFIG_BOOT_NAND
*mcfg = MICRON_V_MCFG_200(512 << 20); *mcfg = MICRON_V_MCFG_200(256 << 20);
*ctrla = MICRON_V_ACTIMA_200; *ctrla = MICRON_V_ACTIMA_200;
*ctrlb = MICRON_V_ACTIMB_200; *ctrlb = MICRON_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
#else #else
if (get_cpu_family() == CPU_OMAP34XX) { if (get_cpu_family() == CPU_OMAP34XX) {
*mcfg = NUMONYX_V_MCFG_165(512 << 20); *mcfg = NUMONYX_V_MCFG_165(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_165; *ctrla = NUMONYX_V_ACTIMA_165;
*ctrlb = NUMONYX_V_ACTIMB_165; *ctrlb = NUMONYX_V_ACTIMB_165;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
} else { } else {
*mcfg = NUMONYX_V_MCFG_200(512 << 20); *mcfg = NUMONYX_V_MCFG_200(256 << 20);
*ctrla = NUMONYX_V_ACTIMA_200; *ctrla = NUMONYX_V_ACTIMA_200;
*ctrlb = NUMONYX_V_ACTIMB_200; *ctrlb = NUMONYX_V_ACTIMB_200;
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;