mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-10 20:52:22 -04:00
mpc83xx: cosmetic: MPC8323ERDB.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
6f681b7349
commit
4dde49d8cb
@ -69,7 +69,8 @@
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*/
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*/
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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#define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
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#define CONFIG_SYS_SPCR_OPT 1
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/*
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/*
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* DDR Setup
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* DDR Setup
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@ -90,7 +91,8 @@
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#define CONFIG_SYS_DDR_SIZE 64 /* MB */
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#define CONFIG_SYS_DDR_SIZE 64 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_WR_ACS \
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| CSCONFIG_ODT_WR_ACS \
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| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_9)
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/* 0x80010101 */
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/* 0x80010101 */
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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@ -164,7 +166,8 @@
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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/*
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* Local Bus Configuration & Clock Setup
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* Local Bus Configuration & Clock Setup
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@ -182,12 +185,13 @@
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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| (2 << BR_PS_SHIFT) /* 16 bit port */ \
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BR_V) /* valid */
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| BR_V) /* valid */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
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#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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@ -201,7 +205,7 @@
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#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
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#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
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#ifdef CONFIG_SYS_LB_SDRAM
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#ifdef CONFIG_SYS_LB_SDRAM
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base addr */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
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@ -226,7 +230,8 @@
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* the top 17 bits of BR2.
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* the top 17 bits of BR2.
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*/
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*/
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
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/*Port size=32bit, MSEL=SDRAM */
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#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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/*
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/*
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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@ -244,8 +249,10 @@
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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/* LB sdram refresh timer, about 6us */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_LSRT 0x32000000
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/* LB refresh timer prescal, 266MHz/32 */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
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@ -254,7 +261,8 @@
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/*
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/*
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* Windows to access PIB via local bus
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* Windows to access PIB via local bus
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*/
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*/
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#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
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/* windows base 0xf8008000 */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
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/*
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/*
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@ -361,7 +369,8 @@
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*/
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#else
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@ -415,9 +424,11 @@
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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/*
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@ -425,7 +436,8 @@
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* have to be in the first 256 MB of memory, since this is
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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* the maximum mapped by the Linux kernel during initialization.
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*/
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/*
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/*
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* Core HID Setup
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* Core HID Setup
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@ -441,23 +453,40 @@
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR: cache cacheable */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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| BATL_PP_10 \
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
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| BATU_BL_4M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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/* FLASH: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
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| BATL_PP_10 \
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
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| BATL_MEMCOHERENCE)
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
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| BATU_BL_32M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
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| BATL_PP_10 \
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_IBAT3L (0)
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#define CONFIG_SYS_IBAT3L (0)
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@ -467,20 +496,33 @@
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/* Stack in dcache: cacheable, no memory coherence */
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/* Stack in dcache: cacheable, no memory coherence */
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
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| BATU_BL_128K \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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/* PCI MEM space: cacheable */
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/* PCI MEM space: cacheable */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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/* PCI MMIO space: cache-inhibit and guarded */
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/* PCI MMIO space: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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| BATL_PP_10 \
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
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| BATL_CACHEINHIBIT \
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| BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#else
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#else
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#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
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#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
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#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
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#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
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/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
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/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
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#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
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* (see CONFIG_SYS_I2C_EEPROM) */
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/* MAC address offset in I2C EEPROM */
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#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
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#define CONFIG_NETDEV eth1
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#define CONFIG_NETDEV "eth1"
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#define CONFIG_HOSTNAME mpc8323erdb
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#define CONFIG_HOSTNAME mpc8323erdb
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#define CONFIG_ROOTPATH "/nfsroot"
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#define CONFIG_ROOTPATH "/nfsroot"
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#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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/* U-Boot image on TFTP server */
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#define CONFIG_FDTFILE mpc832x_rdb.dtb
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#define CONFIG_UBOOTPATH "u-boot.bin"
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#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
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#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 800000
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#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
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#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BAUDRATE 115200
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#define MK_STR(x) XMK_STR(x)
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#define MK_STR(x) XMK_STR(x)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
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"netdev=" CONFIG_NETDEV "\0" \
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"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
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"uboot=" CONFIG_UBOOTPATH "\0" \
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"tftpflash=tftp $loadaddr $uboot;" \
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"tftpflash=tftp $loadaddr $uboot;" \
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"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
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"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
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"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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@ -542,14 +588,15 @@
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"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
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"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
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"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
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"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
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"fdtaddr=780000\0" \
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"fdtaddr=780000\0" \
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"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
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"fdtfile=" CONFIG_FDTFILE "\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
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"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
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"console=ttyS0\0" \
|
"console=ttyS0\0" \
|
||||||
"setbootargs=setenv bootargs " \
|
"setbootargs=setenv bootargs " \
|
||||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
|
||||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
|
||||||
|
"$netdev:off "\
|
||||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
||||||
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \
|
#define CONFIG_NFSBOOTCOMMAND \
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user