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omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF
When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini <trini@ti.com>
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@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
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/* Declarations */
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/* Declarations */
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extern omap3_sysinfo sysinfo;
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extern omap3_sysinfo sysinfo;
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static void omap3_setup_aux_cr(void);
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static void omap3_setup_aux_cr(void);
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#ifndef CONFIG_SYS_L2CACHE_OFF
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static void omap3_invalidate_l2_cache_secure(void);
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static void omap3_invalidate_l2_cache_secure(void);
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#endif
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static const struct gpio_bank gpio_bank_34xx[6] = {
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static const struct gpio_bank gpio_bank_34xx[6] = {
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{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
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@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
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}
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}
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}
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}
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static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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/* Write ACR - affects non-secure banked bits */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
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}
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static void omap3_setup_aux_cr(void)
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static void omap3_setup_aux_cr(void)
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{
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{
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/* Workaround for Cortex-A8 errata: #454179 #430973
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/* Workaround for Cortex-A8 errata: #454179 #430973
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@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
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}
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}
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#ifndef CONFIG_SYS_L2CACHE_OFF
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#ifndef CONFIG_SYS_L2CACHE_OFF
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static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
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{
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u32 acr;
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/* Read ACR */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
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acr &= ~clear_bits;
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acr |= set_bits;
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/* Write ACR - affects non-secure banked bits */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
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}
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/* Invalidate the entire L2 cache from secure mode */
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/* Invalidate the entire L2 cache from secure mode */
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static void omap3_invalidate_l2_cache_secure(void)
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static void omap3_invalidate_l2_cache_secure(void)
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{
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{
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