From 89188a62333c0841a7166783d2ebdd39d7044eb2 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Wed, 15 Jul 2009 08:54:50 -0500
Subject: [PATCH 01/13] 85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards

We have always mapped at least 16M in the kernel and we have seen cases
with new kernel features that a kernel image needs more than 8M of
memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8536DS.h  | 4 ++--
 include/configs/MPC8540ADS.h | 4 ++--
 include/configs/MPC8541CDS.h | 4 ++--
 include/configs/MPC8544DS.h  | 4 ++--
 include/configs/MPC8548CDS.h | 4 ++--
 include/configs/MPC8555CDS.h | 4 ++--
 include/configs/MPC8560ADS.h | 4 ++--
 include/configs/MPC8568MDS.h | 4 ++--
 include/configs/MPC8569MDS.h | 4 ++--
 include/configs/MPC8572DS.h  | 4 ++--
 include/configs/P2020DS.h    | 4 ++--
 11 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 7085d287d..bd81532c8 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -563,10 +563,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 525361179..4af599b1b 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -418,10 +418,10 @@
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 813512c04..a8f206f53 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -440,10 +440,10 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 1d8fecf79..8d5cfa117 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -458,10 +458,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 7089ac77e..bebb9e961 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -500,10 +500,10 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index ef95118ff..94952dc99 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -438,10 +438,10 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 761a370d1..c1a1a6d92 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -452,10 +452,10 @@
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index ac3404737..7b8c6c772 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -456,10 +456,10 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 27044f7bb..6e8f1ff60 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -471,10 +471,10 @@ extern unsigned long get_clock_freq(void);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
 					/* Initial Memory map for Linux*/
 
 /*
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 235be5143..83f9ca901 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -607,10 +607,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index 70ab96f33..d4b48d041 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -636,10 +636,10 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Internal Definitions

From 9af9c6bdc16da53772c56b1a79c2c91701fe94e6 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Wed, 15 Jul 2009 13:45:00 -0500
Subject: [PATCH 02/13] 86xx: Report which "bank" of NOR flash we are booting
 from on MPC8641HPCN

The MPC8641HPCN board is capable of swizzling the upper address bit of
the NOR flash we boot out of which creates the concept of "virtual"
banks.  This is useful in that we can flash a test of image of u-boot
and reset to one of the virtual banks while still maintaining a
working image in "bank 0".

The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8641hpcn/mpc8641hpcn.c | 18 ++++++++++++++----
 include/configs/MPC8641HPCN.h             |  2 ++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 7422e6b9d..441127bbf 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -42,10 +42,20 @@ int board_early_init_f(void)
 
 int checkboard(void)
 {
-	printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
-		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	if (vboot & PIXIS_VBOOT_FMAP)
+		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+	else
+		puts ("Promjet\n");
+
 #ifdef CONFIG_PHYS_64BIT
 	printf ("       36-bit physical address map\n");
 #endif
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 955ac3dfa..bf2e359fd 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -224,6 +224,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */

From 6bb5b412291177e6edd42f9a80e5c5afe57a6a0f Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Tue, 14 Jul 2009 22:42:01 -0500
Subject: [PATCH 03/13] 85xx: Report which "bank" of NOR flash we are booting
 from on FSL boards

The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks.  This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".

The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8536ds/mpc8536ds.c | 39 ++++++++++++++++++++++++---
 board/freescale/mpc8544ds/mpc8544ds.c | 16 ++++++++---
 board/freescale/mpc8572ds/mpc8572ds.c | 26 +++++++++++++++---
 board/freescale/p2020ds/p2020ds.c     | 23 +++++++++++++---
 include/configs/MPC8536DS.h           |  7 +++++
 include/configs/MPC8544DS.h           |  2 ++
 include/configs/MPC8572DS.h           |  5 ++++
 include/configs/P2020DS.h             |  5 ++++
 8 files changed, 109 insertions(+), 14 deletions(-)

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 28b27ee8f..66f095f7a 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -60,10 +60,41 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	printf ("Board: MPC8536DS, System ID: 0x%02x, "
-		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	puts("Board: MPC8536DS ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+
+	printf ("Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
+		case PIXIS_VBOOT_LBMAP_NOR0:
+			puts ("vBank: 0\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR1:
+			puts ("vBank: 1\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR2:
+			puts ("vBank: 2\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR3:
+			puts ("vBank: 3\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_PJET:
+			puts ("Promjet\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NAND:
+			puts ("NAND\n");
+			break;
+	}
+
 	return 0;
 }
 
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 34bdbade7..b251e2e58 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -43,14 +43,22 @@ int checkboard (void)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
 	}
-	printf ("Board: MPC8544DS, System ID: 0x%02x, "
-		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	if (vboot & PIXIS_VBOOT_FMAP)
+		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+	else
+		puts ("Promjet\n");
 
 	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
 	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 4b956171f..51231d7a4 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -42,14 +42,34 @@ long int fixed_sdram(void);
 
 int checkboard (void)
 {
+	u8 vboot;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	puts ("Board: MPC8572DS ");
 #ifdef CONFIG_PHYS_64BIT
 	puts ("(36-bit addrmap) ");
 #endif
 	printf ("Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	vboot = in_8(pixis_base + PIXIS_VBOOT);
+	switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
+		case PIXIS_VBOOT_LBMAP_NOR0:
+			puts ("vBank: 0\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_PJET:
+			puts ("Promjet\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NAND:
+			puts ("NAND\n");
+			break;
+		case PIXIS_VBOOT_LBMAP_NOR1:
+			puts ("vBank: 1\n");
+			break;
+	}
+
 	return 0;
 }
 
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 293e5a42d..fdd832554 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -47,14 +47,31 @@ phys_size_t fixed_sdram(void);
 
 int checkboard(void)
 {
+	u8 sw7;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	puts("Board: P2020DS ");
 #ifdef CONFIG_PHYS_64BIT
 	puts("(36-bit addrmap) ");
 #endif
+
 	printf("Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
+
+	sw7 = in_8(pixis_base + PIXIS_SW(7));
+	switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
+		case 0:
+		case 1:
+			printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
+			break;
+		case 2:
+		case 3:
+			puts ("Promjet\n");
+			break;
+	}
+
 	return 0;
 }
 
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index bd81532c8..2cbc6c70a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -218,6 +218,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
+#define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 8d5cfa117..2efeb72e6 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -192,6 +192,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 83f9ca901..64f5c4b75 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -237,6 +237,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index d4b48d041..5c2c5cb32 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -282,6 +282,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define PIXIS_VWATCH		0x24	/* Watchdog Register */
 #define PIXIS_LED		0x25	/* LED Register */
 
+#define PIXIS_SW(x)		0x20 + (x - 1) * 2
+#define PIXIS_EN(x)		0x21 + (x - 1) * 2
+#define PIXIS_SW7_LBMAP		0xc0	/* SW7 - cfg_lbmap */
+#define PIXIS_SW7_VBANK		0x30	/* SW7 - cfg_vbank */
+
 /* old pixis referenced names */
 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */

From f6155c6fbb1d85f517b7c160570f0995ef14c43f Mon Sep 17 00:00:00 2001
From: Roy Zang <tie-fei.zang@freescale.com>
Date: Thu, 9 Jul 2009 10:05:48 +0800
Subject: [PATCH 04/13] 85xx: Add pci/pcie E1000 ethernet support for MPC8544DS
 and MPC8536 boards

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8536DS.h | 1 +
 include/configs/MPC8544DS.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2cbc6c70a..0aaab4a4a 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -45,6 +45,7 @@
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index 2efeb72e6..2de313931 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -44,6 +44,7 @@
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
 
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE

From e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 17 Jul 2009 10:14:45 -0500
Subject: [PATCH 05/13] 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1
 fields

Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8610hpcd/mpc8610hpcd.c |  4 ++--
 board/freescale/mpc8641hpcn/mpc8641hpcn.c |  6 +++---
 board/sbc8641d/sbc8641d.c                 | 12 ++++++------
 cpu/mpc86xx/ddr-8641.c                    |  4 ++--
 include/asm-ppc/immap_86xx.h              |  4 ++--
 5 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index a85ebead5..419b2c191 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -154,7 +154,7 @@ phys_size_t fixed_sdram(void)
 	ddr->timing_cfg_0 = 0x00260802;
 	ddr->timing_cfg_1 = 0x3935d322;
 	ddr->timing_cfg_2 = 0x14904cc8;
-	ddr->sdram_mode_1 = 0x00480432;
+	ddr->sdram_mode = 0x00480432;
 	ddr->sdram_mode_2 = 0x00000000;
 	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 	ddr->sdram_data_init = 0xDEADBEEF;
@@ -170,7 +170,7 @@ phys_size_t fixed_sdram(void)
 
 	udelay(500);
 
-	ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
 
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 441127bbf..ce2632078 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -101,7 +101,7 @@ fixed_sdram(void)
 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
@@ -119,9 +119,9 @@ fixed_sdram(void)
 
 #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 #else
-	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 #endif
 	asm("sync; isync");
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index c39d2c020..f118a6eaa 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -127,9 +127,9 @@ long int fixed_sdram (void)
 	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
-	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
 	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
@@ -140,7 +140,7 @@ long int fixed_sdram (void)
 
 	udelay (500);
 
-	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
 	asm ("sync; isync");
 
 	udelay (500);
@@ -158,9 +158,9 @@ long int fixed_sdram (void)
 	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
 	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
 	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
-	ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
 	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
-	ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+	ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
 	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
 	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
 	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
@@ -171,7 +171,7 @@ long int fixed_sdram (void)
 
 	udelay (500);
 
-	ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
+	ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
 	asm ("sync; isync");
 
 	udelay (500);
diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c
index 51d0102ce..b8f2c9387 100644
--- a/cpu/mpc86xx/ddr-8641.c
+++ b/cpu/mpc86xx/ddr-8641.c
@@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-	out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
+	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 	out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
@@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	udelay(200);
 	asm volatile("sync;isync");
 
-	out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
+	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
 
 	/*
 	 * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a8398348b..fdfc654f2 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -114,9 +114,9 @@ typedef struct ccsr_ddr {
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
-	uint	sdram_cfg_1;		/* 0x2110 - DDR SDRAM Control Configuration 1 */
+	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration 1 */
 	uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
-	uint	sdram_mode_1;		/* 0x2118 - DDR SDRAM Mode Configuration 1 */
+	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration 1 */
 	uint    sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2 */
 	uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
 	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */

From ed2c9488bbe389b7b25cada1e42bdae5d0976327 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 17 Jul 2009 10:14:46 -0500
Subject: [PATCH 06/13] xes: Remove 8xxx board_add_ram_info() function

This is in preparation for adding one common 8xxx board_add_ram_info()
fuction for all 8xxx boards

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/xes/common/fsl_8xxx_ddr.c | 53 ---------------------------------
 1 file changed, 53 deletions(-)

diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c
index ec64efaba..81ee70d5a 100644
--- a/board/xes/common/fsl_8xxx_ddr.c
+++ b/board/xes/common/fsl_8xxx_ddr.c
@@ -44,56 +44,3 @@ phys_size_t initdram(int board_type)
 
 	return dram_size;
 }
-
-#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
-void board_add_ram_info(int use_default)
-{
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-#if defined(CONFIG_MPC85xx)
-	volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-#elif defined(CONFIG_MPC86xx)
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
-#endif
-#endif
-
-	puts(" (");
-
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
-	/* Print interleaving information */
-	if (ddr1->cs0_config & 0x20000000) {
-		switch ((ddr1->cs0_config >> 24) & 0xf) {
-		case 0:
-			puts("cache line");
-			break;
-		case 1:
-			puts("page");
-			break;
-		case 2:
-			puts("bank");
-			break;
-		case 3:
-			puts("super-bank");
-			break;
-		default:
-			puts("invalid");
-			break;
-		}
-	} else {
-		puts("no");
-	}
-
-	puts(" interleaving");
-#endif
-
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
-	puts(", ");
-#endif
-
-#if defined(CONFIG_DDR_ECC)
-	puts("ECC enabled");
-#endif
-
-	puts(")");
-}
-#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */

From 12a440ae6d09445140f1a0c2023dba76a9f1a617 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 17 Jul 2009 10:14:47 -0500
Subject: [PATCH 07/13] tqm85xx: Remove board_add_ram_info()

This is in preparation for adding one common 8xxx board_add_ram_info()
function for all 8xxx boards

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/tqc/tqm85xx/sdram.c | 33 +++------------------------------
 1 file changed, 3 insertions(+), 30 deletions(-)

diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 6d73a88ab..503c5e530 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -374,31 +374,6 @@ long int sdram_setup (int casl)
 	return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
 }
 
-void board_add_ram_info (int use_default)
-{
-	int casl;
-
-	if (use_default)
-		casl = CONFIG_DDR_DEFAULT_CL;
-	else
-		casl = cas_latency ();
-
-	puts (" (CL=");
-	switch (casl) {
-	case 20:
-		puts ("2)");
-		break;
-
-	case 25:
-		puts ("2.5)");
-		break;
-
-	case 30:
-		puts ("3)");
-		break;
-	}
-}
-
 phys_size_t initdram (int board_type)
 {
 	long dram_size = 0;
@@ -438,11 +413,9 @@ phys_size_t initdram (int board_type)
 		/*
 		 * Try again with default CAS latency
 		 */
-		puts ("Problem with CAS lantency");
-		board_add_ram_info (1);
-		puts (", using default CL!\n");
-		casl = CONFIG_DDR_DEFAULT_CL;
-		dram_size = sdram_setup (casl);
+		printf ("Problem with CAS lantency, using default CL %d/10!\n",
+			CONFIG_DDR_DEFAULT_CL);
+		dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
 		puts ("       ");
 	}
 

From d9c147f371800a479a507a816b2fe572c97da197 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 17 Jul 2009 10:14:48 -0500
Subject: [PATCH 08/13] 85xx, 86xx: Add common board_add_ram_info()

Previously, 85xx and 86xx boards would display DRAM information on
bootup such as:

...
I2C:   ready
DRAM:
Memory controller interleaving enabled: Bank interleaving!
 2 GB
FLASH: 256 MB
...

This patch moves the printing of the DRAM controller configuration to a
common board_add_ram_info() function which prints out DDR type, width,
CAS latency, and ECC mode.  It also makes the DDR interleaving
information print out in a more sane manner:

...
I2C:   ready
DRAM:   2 GB (DDR2, 64-bit, CL=4, ECC on)
       DDR Controller Interleaving Mode: bank
FLASH: 256 MB
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc8xxx/ddr/main.c | 43 +------------------
 cpu/mpc8xxx/ddr/util.c | 96 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 98 insertions(+), 41 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 6dae26bd3..faa1af95e 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -162,28 +162,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			j++;
 		}
 	}
-	if (j == 2) {
+	if (j == 2)
 		*memctl_interleaving = 1;
 
-		printf("\nMemory controller interleaving enabled: ");
-
-		switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
-		case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			printf("Cache-line interleaving!\n");
-			break;
-		case FSL_DDR_PAGE_INTERLEAVING:
-			printf("Page interleaving!\n");
-			break;
-		case FSL_DDR_BANK_INTERLEAVING:
-			printf("Bank interleaving!\n");
-			break;
-		case FSL_DDR_SUPERBANK_INTERLEAVING:
-			printf("Super bank interleaving\n");
-		default:
-			break;
-		}
-	}
-
 	/* Check that all controllers are rank interleaving. */
 	j = 0;
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
@@ -191,29 +172,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			j++;
 		}
 	}
-	if (j == 2) {
+	if (j == 2)
 		*rank_interleaving = 1;
 
-		printf("Bank(chip-select) interleaving enabled: ");
-
-		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
-						FSL_DDR_CS0_CS1_CS2_CS3) {
-		case FSL_DDR_CS0_CS1_CS2_CS3:
-			printf("CS0+CS1+CS2+CS3\n");
-			break;
-		case FSL_DDR_CS0_CS1:
-			printf("CS0+CS1\n");
-			break;
-		case FSL_DDR_CS2_CS3:
-			printf("CS2+CS3\n");
-			break;
-		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-			printf("CS0+CS1 and CS2+CS3\n");
-		default:
-			break;
-		}
-	}
-
 	if (*memctl_interleaving) {
 		unsigned long long addr, total_mem_per_ctlr = 0;
 		/*
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c
index 70dbee06d..4451989a0 100644
--- a/cpu/mpc8xxx/ddr/util.c
+++ b/cpu/mpc8xxx/ddr/util.c
@@ -107,3 +107,99 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 			 unsigned int memctl_interleaved,
 			 unsigned int ctrl_num);
+
+void board_add_ram_info(int use_default)
+{
+#if defined(CONFIG_MPC85xx)
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#elif defined(CONFIG_MPC86xx)
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	uint32_t cs0_config = in_be32(&ddr->cs0_config);
+#endif
+	uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
+	int cas_lat;
+
+	puts(" (DDR");
+	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
+	case SDRAM_TYPE_DDR1:
+		puts("1");
+		break;
+	case SDRAM_TYPE_DDR2:
+		puts("2");
+		break;
+	case SDRAM_TYPE_DDR3:
+		puts("3");
+		break;
+	default:
+		puts("?");
+		break;
+	}
+
+	if (sdram_cfg & SDRAM_CFG_32_BE)
+		puts(", 32-bit");
+	else
+		puts(", 64-bit");
+
+	/* Calculate CAS latency based on timing cfg values */
+	cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+	if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
+		cas_lat += (8 << 1);
+	printf(", CL=%d", cas_lat >> 1);
+	if (cas_lat & 0x1)
+		puts(".5");
+
+	if (sdram_cfg & SDRAM_CFG_ECC_EN)
+		puts(", ECC on)");
+	else
+		puts(", ECC off)");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	if (cs0_config & 0x20000000) {
+		puts("\n");
+		puts("       DDR Controller Interleaving Mode: ");
+
+		switch ((cs0_config >> 24) & 0xf) {
+		case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			puts("cache line");
+			break;
+		case FSL_DDR_PAGE_INTERLEAVING:
+			puts("page");
+			break;
+		case FSL_DDR_BANK_INTERLEAVING:
+			puts("bank");
+			break;
+		case FSL_DDR_SUPERBANK_INTERLEAVING:
+			puts("super-bank");
+			break;
+		default:
+			puts("invalid");
+			break;
+		}
+	}
+#endif
+
+	if ((sdram_cfg >> 8) & 0x7f) {
+		puts("\n");
+		puts("       DDR Chip-Select Interleaving Mode: ");
+		switch(sdram_cfg >> 8 & 0x7f) {
+		case FSL_DDR_CS0_CS1_CS2_CS3:
+			puts("CS0+CS1+CS2+CS3");
+			break;
+		case FSL_DDR_CS0_CS1:
+			puts("CS0+CS1");
+			break;
+		case FSL_DDR_CS2_CS3:
+			puts("CS2+CS3");
+			break;
+		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+			puts("CS0+CS1 and CS2+CS3");
+			break;
+		default:
+			puts("invalid");
+			break;
+		}
+	}
+}

From 5ff821006c6e7647d183ea95817044943bb22e7e Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Sun, 19 Jul 2009 19:17:40 -0500
Subject: [PATCH 09/13] xpedite5200,5370: Use buffered NOR flash writes

Buffered writes are possible on the XPedite5200 and XPedite5370 and greatly
improve NOR flash write speeds

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/XPEDITE5200.h | 1 +
 include/configs/XPEDITE5370.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 89ab69272..617f514ab 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -129,6 +129,7 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
 						  {0xfbf40000, 0xc0000} }
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 536e06338..d00448baf 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -137,6 +137,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
 						  {0xf7f40000, 0xc0000} }
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */

From 58f31b602dfd52eb7836ab82caa587514e046f02 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Sun, 19 Jul 2009 19:17:41 -0500
Subject: [PATCH 10/13] xpedite5370: Fix I2C GPIO initialization typo

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Heiko Schocher<hs@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/xes/xpedite5370/xpedite5370.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c
index 22cf29431..d54c69972 100644
--- a/board/xes/xpedite5370/xpedite5370.c
+++ b/board/xes/xpedite5370/xpedite5370.c
@@ -84,8 +84,8 @@ int board_early_init_r(void)
 	/* Initialize PCA9557 devices */
 	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
 	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
-	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+	pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
 
 	/*
 	 * Remap NOR flash region to caching-inhibited

From 39121c0896a6760bd436d88c17892f49a97902d0 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Tue, 21 Jul 2009 13:51:07 -0500
Subject: [PATCH 11/13] xes: Increase CONFIG_SYS_BOOTM_LEN to 16MB

Increasing CONFIG_SYS_BOOTM_LEN from 8 MB to 16 MB is necessary to
support uncompressing images larger than 8 MB when using the bootm
command.

Note that recent Linux kernels for the 85xx and 86xx map greater than
16MB of memory on bootup, but we use 16MB to maintain compatibility with
older Linux kernels for now.

Signed-off-by: Nate Case <ncase@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/XPEDITE5170.h | 1 +
 include/configs/XPEDITE5200.h | 1 +
 include/configs/XPEDITE5370.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 985b5893b..8be9fa055 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -579,6 +579,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
 
 /*
  * Boot Flags
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 617f514ab..deda20843 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -370,6 +370,7 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
 
 /*
  * Boot Flags
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index d00448baf..83f50c491 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -413,6 +413,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
 
 /*
  * Boot Flags

From 0a6d0c6320b77bd6572393a93e6b8ccdf39c7100 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Tue, 21 Jul 2009 13:51:08 -0500
Subject: [PATCH 12/13] xpedite5370: Enable NAND command support

Use the MPC8572's eLBC to access 1 GB (or greater) onboard NAND flash
via the 'nand' command.

Previously, the XPedite5370's NAND chip selects were properly
configured, but NAND support was not enabled.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/XPEDITE5370.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 83f50c491..acb62ad1d 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -124,6 +124,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_NAND_BASE		0xef800000
 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST	/* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
 
 /*
  * NOR flash configuration
@@ -375,16 +381,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_SNTP
 
 /*

From 048e7efe91f66094f868281c12e488ce2bae8976 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Wed, 22 Jul 2009 10:12:39 -0500
Subject: [PATCH 13/13] 85xx/86xx: Replace in8/out8 with in_8/out_8 on FSL
 boards

The pixis code used in8/out8 all over the place.  Replace it with
in_8/out_8 macros.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/common/pixis.c                | 78 +++++++++++--------
 board/freescale/mpc8536ds/mpc8536ds.c         | 22 ++++--
 board/freescale/mpc8544ds/mpc8544ds.c         | 11 +--
 board/freescale/mpc8572ds/mpc8572ds.c         | 22 ++++--
 board/freescale/mpc8610hpcd/mpc8610hpcd.c     | 25 +++---
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 13 ++--
 board/freescale/mpc8641hpcn/mpc8641hpcn.c     | 15 ++--
 board/freescale/p2020ds/p2020ds.c             | 22 ++++--
 8 files changed, 122 insertions(+), 86 deletions(-)

diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 4851f066e..7210512bf 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -39,7 +39,8 @@ static ulong strfractoint(uchar *strptr);
  */
 void pixis_reset(void)
 {
-    out8(PIXIS_BASE + PIXIS_RST, 0);
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+	out_8(pixis_base + PIXIS_RST, 0);
 }
 
 
@@ -49,6 +50,7 @@ void pixis_reset(void)
 int set_px_sysclk(ulong sysclk)
 {
 	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	switch (sysclk) {
 	case 33:
@@ -107,10 +109,10 @@ int set_px_sysclk(ulong sysclk)
 	vclkh = (sysclk_s << 5) | sysclk_r;
 	vclkl = sysclk_v;
 
-	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
-	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+	out_8(pixis_base + PIXIS_VCLKH, vclkh);
+	out_8(pixis_base + PIXIS_VCLKL, vclkl);
 
-	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+	out_8(pixis_base + PIXIS_AUX, sysclk_aux);
 
 	return 1;
 }
@@ -120,6 +122,7 @@ int set_px_mpxpll(ulong mpxpll)
 {
 	u8 tmp;
 	u8 val;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	switch (mpxpll) {
 	case 2:
@@ -137,9 +140,9 @@ int set_px_mpxpll(ulong mpxpll)
 		return 0;
 	}
 
-	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+	tmp = in_8(pixis_base + PIXIS_VSPEED1);
 	tmp = (tmp & 0xF0) | (val & 0x0F);
-	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+	out_8(pixis_base + PIXIS_VSPEED1, tmp);
 
 	return 1;
 }
@@ -149,6 +152,7 @@ int set_px_corepll(ulong corepll)
 {
 	u8 tmp;
 	u8 val;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	switch ((int)corepll) {
 	case 20:
@@ -174,9 +178,9 @@ int set_px_corepll(ulong corepll)
 		return 0;
 	}
 
-	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+	tmp = in_8(pixis_base + PIXIS_VSPEED0);
 	tmp = (tmp & 0xE0) | (val & 0x1F);
-	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+	out_8(pixis_base + PIXIS_VSPEED0, tmp);
 
 	return 1;
 }
@@ -184,27 +188,29 @@ int set_px_corepll(ulong corepll)
 
 void read_from_px_regs(int set)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	u8 mask = 0x1C;	/* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
-	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
 
 	if (set)
 		tmp = tmp | mask;
 	else
 		tmp = tmp & ~mask;
-	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+	out_8(pixis_base + PIXIS_VCFGEN0, tmp);
 }
 
 
 void read_from_px_regs_altbank(int set)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	u8 mask = 0x04;	/* FLASHBANK and FLASHMAP controlled by PIXIS */
-	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+	u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
 
 	if (set)
 		tmp = tmp | mask;
 	else
 		tmp = tmp & ~mask;
-	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+	out_8(pixis_base + PIXIS_VCFGEN1, tmp);
 }
 
 #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
@@ -214,50 +220,54 @@ void read_from_px_regs_altbank(int set)
 void clear_altbank(void)
 {
 	u8 tmp;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+	tmp = in_8(pixis_base + PIXIS_VBOOT);
 	tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
 
-	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+	out_8(pixis_base + PIXIS_VBOOT, tmp);
 }
 
 
 void set_altbank(void)
 {
 	u8 tmp;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+	tmp = in_8(pixis_base + PIXIS_VBOOT);
 	tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
 
-	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+	out_8(pixis_base + PIXIS_VBOOT, tmp);
 }
 
 
 void set_px_go(void)
 {
 	u8 tmp;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp = tmp & 0x1E;			/* clear GO bit */
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp = tmp | 0x01;	/* set GO bit - start reset sequencer */
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 }
 
 
 void set_px_go_with_watchdog(void)
 {
 	u8 tmp;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp = tmp & 0x1E;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp = tmp | 0x09;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 }
 
 
@@ -265,15 +275,16 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
 			       int flag, int argc, char *argv[])
 {
 	u8 tmp;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp = tmp & 0x1E;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 
 	/* setting VCTL[WDEN] to 0 to disable watch dog */
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = in_8(pixis_base + PIXIS_VCTL);
 	tmp &= ~0x08;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+	out_8(pixis_base + PIXIS_VCTL, tmp);
 
 	return 0;
 }
@@ -288,6 +299,7 @@ U_BOOT_CMD(
 int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int which_tsec = -1;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 	uchar mask;
 	uchar switch_mask;
 
@@ -328,17 +340,15 @@ int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	/* Toggle whether the switches or FPGA control the settings */
 	if (!strcmp(argv[argc - 1], "switch"))
-		clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
-			switch_mask);
+		clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
 	else
-		setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
-			switch_mask);
+		setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
 
 	/* If it's not the switches, enable or disable SGMII, as specified */
 	if (!strcmp(argv[argc - 1], "on"))
-		clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+		clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
 	else if (!strcmp(argv[argc - 1], "off"))
-		setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
+		setbits_8(pixis_base + PIXIS_VSPEED2, mask);
 
 	return 0;
 }
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 66f095f7a..8c5984bf5 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -529,20 +529,24 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 unsigned long
 get_board_sys_clk(ulong dummy)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	return ics307_clk_freq (
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK0),
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK1),
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK2)
+	    in_8(pixis_base + PIXIS_VSYSCLK0),
+	    in_8(pixis_base + PIXIS_VSYSCLK1),
+	    in_8(pixis_base + PIXIS_VSYSCLK2)
 	);
 }
 
 unsigned long
 get_board_ddr_clk(ulong dummy)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	return ics307_clk_freq (
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK0),
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK1),
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK2)
+	    in_8(pixis_base + PIXIS_VDDRCLK0),
+	    in_8(pixis_base + PIXIS_VDDRCLK1),
+	    in_8(pixis_base + PIXIS_VDDRCLK2)
 	);
 }
 #else
@@ -551,8 +555,9 @@ get_board_sys_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x07;
 
 	switch (i) {
@@ -590,8 +595,9 @@ get_board_ddr_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x38;
 	i >>= 3;
 
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index b251e2e58..fd59839b3 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -391,11 +391,12 @@ get_board_sys_clk(ulong dummy)
 {
 	u8 i, go_bit, rd_clks;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+	go_bit = in_8(pixis_base + PIXIS_VCTL);
 	go_bit &= 0x01;
 
-	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 	rd_clks &= 0x1C;
 
 	/*
@@ -406,11 +407,11 @@ get_board_sys_clk(ulong dummy)
 
 	if (go_bit) {
 		if (rd_clks == 0x1c)
-			i = in8(PIXIS_BASE + PIXIS_AUX);
+			i = in_8(pixis_base + PIXIS_AUX);
 		else
-			i = in8(PIXIS_BASE + PIXIS_SPD);
+			i = in_8(pixis_base + PIXIS_SPD);
 	} else {
-		i = in8(PIXIS_BASE + PIXIS_SPD);
+		i = in_8(pixis_base + PIXIS_SPD);
 	}
 
 	i &= 0x07;
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 51231d7a4..7c86134d5 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -432,19 +432,23 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 
 unsigned long get_board_sys_clk(ulong dummy)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	return ics307_clk_freq (
-			in8(PIXIS_BASE + PIXIS_VSYSCLK0),
-			in8(PIXIS_BASE + PIXIS_VSYSCLK1),
-			in8(PIXIS_BASE + PIXIS_VSYSCLK2)
+			in_8(pixis_base + PIXIS_VSYSCLK0),
+			in_8(pixis_base + PIXIS_VSYSCLK1),
+			in_8(pixis_base + PIXIS_VSYSCLK2)
 			);
 }
 
 unsigned long get_board_ddr_clk(ulong dummy)
 {
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	return ics307_clk_freq (
-			in8(PIXIS_BASE + PIXIS_VDDRCLK0),
-			in8(PIXIS_BASE + PIXIS_VDDRCLK1),
-			in8(PIXIS_BASE + PIXIS_VDDRCLK2)
+			in_8(pixis_base + PIXIS_VDDRCLK0),
+			in_8(pixis_base + PIXIS_VDDRCLK1),
+			in_8(pixis_base + PIXIS_VDDRCLK2)
 			);
 }
 #else
@@ -452,8 +456,9 @@ unsigned long get_board_sys_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x07;
 
 	switch (i) {
@@ -490,8 +495,9 @@ unsigned long get_board_ddr_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x38;
 	i >>= 3;
 
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 419b2c191..2ac169b79 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -55,16 +55,17 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 	u8 tmp_val, version;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	/*Do not use 8259PIC*/
-	tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
-	out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
+	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
 
 	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
-	version = in8(PIXIS_BASE + PIXIS_PVER);
+	version = in_8(pixis_base + PIXIS_PVER);
 	if(version >= 0x07) {
-		tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
-		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
+		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
 	}
 
 	/* Using this for DIU init before the driver in linux takes over
@@ -96,11 +97,12 @@ int checkboard(void)
 {
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
 	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
 		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
-		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
-		in8(PIXIS_BASE + PIXIS_PVER));
+		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+		in_8(pixis_base + PIXIS_PVER));
 
 	mcm->abcr |= 0x00010000; /* 0 */
 	mcm->hpmr3 = 0x80000008; /* 4c */
@@ -438,10 +440,9 @@ get_board_sys_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
-	ulong a;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	a = PIXIS_BASE + PIXIS_SPD;
-	i = in8(a);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x07;
 
 	switch (i) {
@@ -481,7 +482,9 @@ int board_eth_init(bd_t *bis)
 
 void board_reset(void)
 {
-	out8(PIXIS_BASE + PIXIS_RST, 0);
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	out_8(pixis_base + PIXIS_RST, 0);
 
 	while (1)
 		;
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 63eba0c59..4186a2ecd 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -69,9 +69,10 @@ void mpc8610hpcd_diu_init(void)
 	unsigned int pixel_format;
 	unsigned char tmp_val;
 	unsigned char pixis_arch;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
-	pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
+	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+	pixis_arch = in_8(pixis_base + PIXIS_VER);
 
 	monitor_port = getenv("monitor");
 	if (!strncmp(monitor_port, "0", 1)) {	/* 0 - DVI */
@@ -82,28 +83,28 @@ void mpc8610hpcd_diu_init(void)
 		else
 			pixel_format = 0x88883316;
 		gamma_fix = 0;
-		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
 
 	} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
 		xres = 1024;
 		yres = 768;
 		pixel_format = 0x88883316;
 		gamma_fix = 0;
-		out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
+		out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
 
 	} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
 		xres = 1280;
 		yres = 1024;
 		pixel_format = 0x88883316;
 		gamma_fix = 1;
-		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
 
 	} else {	/* DVI */
 		xres = 1280;
 		yres = 1024;
 		pixel_format = 0x88882317;
 		gamma_fix = 0;
-		out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
 	}
 
 	fsl_diu_init(xres, pixel_format, gamma_fix,
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index ce2632078..a8b211226 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -310,11 +310,12 @@ get_board_sys_clk(ulong dummy)
 {
 	u8 i, go_bit, rd_clks;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+	go_bit = in_8(pixis_base + PIXIS_VCTL);
 	go_bit &= 0x01;
 
-	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 	rd_clks &= 0x1C;
 
 	/*
@@ -325,11 +326,11 @@ get_board_sys_clk(ulong dummy)
 
 	if (go_bit) {
 		if (rd_clks == 0x1c)
-			i = in8(PIXIS_BASE + PIXIS_AUX);
+			i = in_8(pixis_base + PIXIS_AUX);
 		else
-			i = in8(PIXIS_BASE + PIXIS_SPD);
+			i = in_8(pixis_base + PIXIS_SPD);
 	} else {
-		i = in8(PIXIS_BASE + PIXIS_SPD);
+		i = in_8(pixis_base + PIXIS_SPD);
 	}
 
 	i &= 0x07;
@@ -373,7 +374,9 @@ int board_eth_init(bd_t *bis)
 
 void board_reset(void)
 {
-	out8(PIXIS_BASE + PIXIS_RST, 0);
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+	out_8(pixis_base + PIXIS_RST, 0);
 
 	while (1)
 		;
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index fdd832554..14de7e740 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -479,10 +479,12 @@ unsigned long
 calculate_board_sys_clk(ulong dummy)
 {
 	ulong val;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	val = ics307_clk_freq(
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK0),
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK1),
-	    in8(PIXIS_BASE + PIXIS_VSYSCLK2));
+	    in_8(pixis_base + PIXIS_VSYSCLK0),
+	    in_8(pixis_base + PIXIS_VSYSCLK1),
+	    in_8(pixis_base + PIXIS_VSYSCLK2));
 	debug("sysclk val = %lu\n", val);
 	return val;
 }
@@ -491,10 +493,12 @@ unsigned long
 calculate_board_ddr_clk(ulong dummy)
 {
 	ulong val;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
+
 	val = ics307_clk_freq(
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK0),
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK1),
-	    in8(PIXIS_BASE + PIXIS_VDDRCLK2));
+	    in_8(pixis_base + PIXIS_VDDRCLK0),
+	    in_8(pixis_base + PIXIS_VDDRCLK1),
+	    in_8(pixis_base + PIXIS_VDDRCLK2));
 	debug("ddrclk val = %lu\n", val);
 	return val;
 }
@@ -503,8 +507,9 @@ unsigned long get_board_sys_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x07;
 
 	switch (i) {
@@ -541,8 +546,9 @@ unsigned long get_board_ddr_clk(ulong dummy)
 {
 	u8 i;
 	ulong val = 0;
+	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i = in_8(pixis_base + PIXIS_SPD);
 	i &= 0x38;
 	i >>= 3;