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powerpc/mpc8548: Add workaround for erratum NMG_DDR120

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Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.

Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-09-16 09:54:30 -05:00
parent 568336ecc7
commit 5ace2992b5
3 changed files with 25 additions and 0 deletions
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4
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -95,6 +95,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
puts("Work-around for Erratum IFC A-003399 enabled\n"); puts("Work-around for Erratum IFC A-003399 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG DDR120 enabled\n");
#endif #endif
return 0; return 0;
} }

20
arch/powerpc/cpu/mpc85xx/ddr-gen2.c
View File

@ -8,6 +8,7 @@
#include <common.h> #include <common.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@ -22,6 +23,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR; ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
#else #else
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint svr;
#endif
#endif #endif
if (ctrl_num) { if (ctrl_num) {
@ -29,6 +34,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
return; return;
} }
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
/*
* Set the DDR IO receiver to an acceptable bias point.
* Fixed in Rev 2.1.
*/
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
SDRAM_CFG_SDRAM_TYPE_DDR2)
out_be32(&gur->ddrioovcr, 0x90000000);
else
out_be32(&gur->ddrioovcr, 0xA8000000);
}
#endif
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) { if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);

1
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -62,6 +62,7 @@
#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#elif defined(CONFIG_MPC8555) #elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1