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ppc4xx: Fix power mgt definitions for PPC440

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Corrected DCR addresses of PPC440EP power management registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
This commit is contained in:
Eugene O'Brien 2008-04-11 10:00:35 -04:00 committed by Stefan Roese
parent 64e541f4c1
commit 5b2052e5f5
1 changed files with 1 additions and 8 deletions
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9
include/ppc440.h
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@ -1731,17 +1731,10 @@
#else #else
#define CNTRL_DCR_BASE 0x0b0 #define CNTRL_DCR_BASE 0x0b0
#endif #endif
#if defined(CONFIG_440GX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
#else
#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
#endif
#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */