mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-01 02:39:02 -04:00
Cleanup whitespaces and style issues.
Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft.
This commit is contained in:
Jon Loeliger
parent
a2320a6bf8
commit
5c9efb36a6
@ -57,9 +57,6 @@ int checkboard (void)
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#ifdef CONFIG_PCI
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/* Sri: Note that at this point we will only test on PCI1
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*/
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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volatile ccsr_pex_t *pex1 = &immap->im_pex1;
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@ -70,13 +67,16 @@ int checkboard (void)
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uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
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if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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if ((io_sel==2 || io_sel==3 || io_sel==5 \
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|| io_sel==6 || io_sel==7 || io_sel==0xF)
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&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
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debug ("PCI-EXPRESS 1: %s \n",
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pex1_agent ? "Agent" : "Host");
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debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
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if (pex1->pme_msg_det) {
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pex1->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
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debug (" with errors. Clearing. Now 0x%08x",
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pex1->pme_msg_det);
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}
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debug ("\n");
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} else {
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@ -120,15 +120,6 @@ initdram(int board_type)
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ddr_enable_ecc(dram_size);
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#endif
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/*
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* Initialize SDRAM. Currently HPCN doesn't have
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* SDRAM but we'll leave this here for now
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* in case someone changes their mind
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*/
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#if !defined(CONFIG_MPC8641HPCN)
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// sdram_init();
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#endif
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puts(" DDR: ");
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return dram_size;
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}
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@ -163,7 +154,7 @@ local_bus_init(void)
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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int testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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@ -198,10 +189,10 @@ int testdram (void)
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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long int fixed_sdram (void)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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long int fixed_sdram(void)
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{
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#if !defined(CFG_RAMBOOT)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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@ -1,5 +1,5 @@
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/*
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* MPC8641 HPCn Device Tree Source
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* MPC8641 HPCN Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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@ -32,8 +32,8 @@
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#include <ft_build.h>
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#endif
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extern unsigned long get_board_sys_clk(ulong dummy);
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// SS: For debug only, remove after use
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static __inline__ unsigned long get_dbat3u (void)
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{
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@ -56,7 +56,6 @@ static __inline__ unsigned long get_msr (void)
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return msr;
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}
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extern unsigned long get_board_sys_clk(ulong dummy);
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int checkcpu (void)
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{
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@ -74,7 +73,7 @@ int checkcpu (void)
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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puts ("CPU:\n");
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puts("CPU:\n");
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printf(" Core: ");
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@ -138,7 +137,7 @@ int checkcpu (void)
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else
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printf("Disabled\n");
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return (0);
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return 0;
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}
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@ -271,8 +270,7 @@ int set_px_corepll(ulong corepll)
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u8 tmp;
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u8 val;
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switch((int)corepll)
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{
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switch ((int)corepll) {
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case 20:
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val = 0x08;
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break;
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@ -424,7 +422,7 @@ ulong strfractoint(uchar *strptr)
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}
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#endif //CONFIG_MPC8641HPCN
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#endif /* CONFIG_MPC8641HPCN */
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/* no generic way to do board reset. simply call soft_reset. */
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@ -435,8 +433,6 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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ulong addr, val;
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ulong corepll;
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#ifdef CFG_RESET_ADDRESS
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addr = CFG_RESET_ADDRESS;
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#else
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@ -468,38 +464,32 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#else /* CONFIG_MPC8641HPCN */
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if(argc > 1)
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{
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if (argc > 1) {
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cmd = argv[1][1];
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switch(cmd)
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{
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switch(cmd) {
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case 'f': /* reset with frequency changed */
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if (argc < 5)
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goto my_usage;
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read_from_px_regs(0);
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val = set_px_sysclk(simple_strtoul(argv[2],NULL,10));
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corepll = strfractoint(argv[3]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[4],NULL,10));
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if(val == 3)
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{
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val = val + set_px_mpxpll(simple_strtoul(argv[4],
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NULL, 10));
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if (val == 3) {
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printf("Setting registers VCFGEN0 and VCTL\n");
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read_from_px_regs(1);
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printf("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
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set_px_go();
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}
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else
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} else
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goto my_usage;
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while(1); /* Not reached */
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while (1); /* Not reached */
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case 'l':
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if(argv[2][1] == 'f')
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{
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if (argv[2][1] == 'f') {
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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/* reset with frequency changed */
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@ -508,23 +498,19 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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corepll = strfractoint(argv[4]);
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val = val + set_px_corepll(corepll);
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val = val + set_px_mpxpll(simple_strtoul(argv[5],NULL,10));
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if(val == 3)
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{
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if (val == 3) {
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printf("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
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set_altbank();
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read_from_px_regs(1);
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read_from_px_regs_altbank(1);
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printf("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
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set_px_go_with_watchdog();
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}
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else
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} else
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goto my_usage;
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while(1); /* Not reached */
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}
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else /* Reset from next bank without changing frequencies */
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{
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} else {
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/* Reset from next bank without changing frequencies */
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read_from_px_regs(0);
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read_from_px_regs_altbank(0);
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if(argc > 2)
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@ -540,14 +526,14 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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default:
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goto my_usage;
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}
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my_usage:
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printf("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
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printf(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
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printf("For example: reset cf 40 2.5 10\n");
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printf("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
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return;
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}
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else
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} else
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out8(PIXIS_BASE+PIXIS_RST,0);
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#endif /* !CONFIG_MPC8641HPCN */
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@ -556,8 +542,6 @@ my_usage:
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Get timebase clock frequency
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*/
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@ -566,24 +550,21 @@ unsigned long get_tbclk(void)
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return ((sys_info.freqSystemBus + 3L) / 4L);
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return (sys_info.freqSystemBus + 3L) / 4L;
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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}
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#endif /* CONFIG_WATCHDOG */
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void) {
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void dma_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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@ -593,7 +574,8 @@ void dma_init(void) {
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return;
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}
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uint dma_check(void) {
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uint dma_check(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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volatile uint status = dma->sr0;
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@ -609,7 +591,8 @@ uint dma_check(void) {
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return status;
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}
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int dma_xfer(void *dest, uint count, void *src) {
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int dma_xfer(void *dest, uint count, void *src)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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@ -622,6 +605,7 @@ int dma_xfer(void *dest, uint count, void *src) {
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asm("sync;isync");
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return dma_check();
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}
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#endif /* CONFIG_DDR_ECC */
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@ -36,12 +36,11 @@
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* initialize a bunch of registers
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*/
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void cpu_init_f (void)
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void cpu_init_f(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_lbc_t *memctl = &immap->im_lbc;
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//u8 val;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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@ -72,12 +71,10 @@ void cpu_init_f (void)
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memctl->br1 = CFG_BR1_PRELIM;
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#endif
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//#if !defined(CONFIG_MPC86xx)
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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memctl->or2 = CFG_OR2_PRELIM;
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memctl->br2 = CFG_BR2_PRELIM;
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#endif
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//#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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memctl->or3 = CFG_OR3_PRELIM;
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@ -123,9 +120,9 @@ void cpu_init_f (void)
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r (void)
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int cpu_init_r(void)
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{
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return (0);
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return 0;
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}
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@ -74,13 +74,12 @@ i2c_init(int speed, int slaveadd)
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}
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static __inline__ int
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i2c_wait4bus (void)
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i2c_wait4bus(void)
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{
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ulong timeval = get_timer (0);
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// debug("I2C: Wait for bus\n");
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while (readb(I2CCSR) & MPC86xx_I2CSR_MBB) {
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if (get_timer (timeval) > TIMEOUT) {
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if (get_timer(timeval) > TIMEOUT) {
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return -1;
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}
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}
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@ -89,14 +88,13 @@ i2c_wait4bus (void)
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}
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static __inline__ int
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i2c_wait (int write)
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i2c_wait(int write)
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{
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u32 csr;
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ulong timeval = get_timer (0);
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do {
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csr = readb(I2CCSR);
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if (!(csr & MPC86xx_I2CSR_MIF))
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continue;
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@ -118,7 +116,7 @@ i2c_wait (int write)
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}
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return 0;
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} while (get_timer (timeval) < TIMEOUT);
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} while (get_timer(timeval) < TIMEOUT);
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debug("i2c_wait: timed out\n");
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return -1;
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@ -127,14 +125,13 @@ i2c_wait (int write)
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static __inline__ int
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i2c_write_addr (u8 dev, u8 dir, int rsta)
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{
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// debug("I2C: Write Addr\n");
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX |
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(rsta?MPC86xx_I2CCR_RSTA:0),
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX
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| (rsta ? MPC86xx_I2CCR_RSTA : 0),
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I2CCCR);
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writeb((dev << 1) | dir, I2CCDR);
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if (i2c_wait (I2C_WRITE) < 0)
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if (i2c_wait(I2C_WRITE) < 0)
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return 0;
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return 1;
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@ -144,14 +141,14 @@ static __inline__ int
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__i2c_write (u8 *data, int length)
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{
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int i;
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// debug("I2C: __i2c_write\n");
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA | MPC86xx_I2CCR_MTX,
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I2CCCR);
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for (i=0; i < length; i++) {
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for (i = 0; i < length; i++) {
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writeb(data[i], I2CCDR);
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if (i2c_wait (I2C_WRITE) < 0)
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if (i2c_wait(I2C_WRITE) < 0)
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break;
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}
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@ -163,33 +160,30 @@ __i2c_read (u8 *data, int length)
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{
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int i;
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
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((length == 1) ? MPC86xx_I2CCR_TXAK : 0),
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA
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| ((length == 1) ? MPC86xx_I2CCR_TXAK : 0),
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I2CCCR);
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/* dummy read */
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readb(I2CCDR);
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// debug("length = %d\n", length);
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for (i=0; i < length; i++) {
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if (i2c_wait (I2C_READ) < 0)
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for (i = 0; i < length; i++) {
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if (i2c_wait(I2C_READ) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA |
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MPC86xx_I2CCR_TXAK,
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_MSTA
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| MPC86xx_I2CCR_TXAK,
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I2CCCR);
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/* Generate stop on last byte */
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if (i == length - 1)
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writeb(MPC86xx_I2CCR_MEN | MPC86xx_I2CCR_TXAK, I2CCCR);
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// debug("I2CCR = 0x%08x\n", readb(I2CCCR));
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data[i] = readb(I2CCDR);
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// debug("data[i] = 0x%08x\n", data[i]);
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}
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// debug("Returning i = %d\n", i);
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return i;
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}
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@ -199,19 +193,19 @@ i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
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int i = 0;
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus () < 0)
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if (i2c_wait4bus() < 0)
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goto exit;
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if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
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if (i2c_write_addr(dev, I2C_WRITE, 0) == 0)
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goto exit;
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||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen)
|
||||
if (__i2c_write(&a[4 - alen], alen) != alen)
|
||||
goto exit;
|
||||
|
||||
if (i2c_write_addr (dev, I2C_READ, 1) == 0)
|
||||
if (i2c_write_addr(dev, I2C_READ, 1) == 0)
|
||||
goto exit;
|
||||
|
||||
i = __i2c_read (data, length);
|
||||
i = __i2c_read(data, length);
|
||||
|
||||
exit:
|
||||
writeb(MPC86xx_I2CCR_MEN, I2CCCR);
|
||||
@ -225,16 +219,16 @@ i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
|
||||
int i = 0;
|
||||
u8 *a = (u8*)&addr;
|
||||
|
||||
if (i2c_wait4bus () < 0)
|
||||
if (i2c_wait4bus() < 0)
|
||||
goto exit;
|
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
|
||||
if (i2c_write_addr(dev, I2C_WRITE, 0) == 0)
|
||||
goto exit;
|
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen)
|
||||
if (__i2c_write(&a[4 - alen], alen) != alen)
|
||||
goto exit;
|
||||
|
||||
i = __i2c_write (data, length);
|
||||
i = __i2c_write(data, length);
|
||||
|
||||
exit:
|
||||
writeb(MPC86xx_I2CCR_MEN, I2CCCR);
|
||||
@ -253,21 +247,21 @@ int i2c_probe (uchar chip)
|
||||
*/
|
||||
udelay(10000);
|
||||
|
||||
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
|
||||
return i2c_read(chip, 0, 1, (char *)&tmp, 1);
|
||||
}
|
||||
|
||||
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
|
||||
{
|
||||
char buf[1];
|
||||
|
||||
i2c_read (i2c_addr, reg, 1, buf, 1);
|
||||
i2c_read(i2c_addr, reg, 1, buf, 1);
|
||||
|
||||
return (buf[0]);
|
||||
return buf[0];
|
||||
}
|
||||
|
||||
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
|
||||
{
|
||||
i2c_write (i2c_addr, reg, 1, &val, 1);
|
||||
i2c_write(i2c_addr, reg, 1, &val, 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
||||
@ -75,7 +75,7 @@ static __inline__ void set_dec (unsigned long val)
|
||||
/* interrupt is not supported yet */
|
||||
int interrupt_init_cpu (unsigned *decrementer_count)
|
||||
{
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -98,7 +98,7 @@ int interrupt_init (void)
|
||||
|
||||
debug("MSR = 0x%08lx, Decrementer reg = 0x%08lx\n", get_msr(), get_dec());
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -113,7 +113,7 @@ int disable_interrupts (void)
|
||||
ulong msr = get_msr ();
|
||||
|
||||
set_msr (msr & ~MSR_EE);
|
||||
return ((msr & MSR_EE) != 0);
|
||||
return (msr & MSR_EE) != 0;
|
||||
}
|
||||
|
||||
|
||||
@ -131,7 +131,6 @@ void
|
||||
timer_interrupt_cpu (struct pt_regs *regs)
|
||||
{
|
||||
/* nothing to do here */
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -170,7 +169,7 @@ void reset_timer (void)
|
||||
|
||||
ulong get_timer (ulong base)
|
||||
{
|
||||
return (timestamp - base);
|
||||
return timestamp - base;
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
@ -185,13 +184,11 @@ void set_timer (ulong t)
|
||||
void
|
||||
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void
|
||||
irq_free_handler(int vec)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* PEX Configuration space access support for MPC85xx PEX Bridge
|
||||
* PEX Configuration space access support for PEX Bridge
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
@ -44,24 +44,25 @@ pci_mpc86xx_init(struct pci_controller *hose)
|
||||
|
||||
ulong addr, data;
|
||||
|
||||
|
||||
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
|
||||
uint devdisr = gur->devdisr;
|
||||
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
|
||||
|
||||
if ((io_sel==2 || io_sel==3 || io_sel==5 || io_sel==6 || io_sel==7 || io_sel==0xF ) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
|
||||
if ((io_sel==2 || io_sel==3 || io_sel==5
|
||||
|| io_sel==6 || io_sel==7 || io_sel==0xF )
|
||||
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)){
|
||||
printf ("PCI-EXPRESS 1: Configured as %s \n",
|
||||
pex1_agent ? "Agent" : "Host");
|
||||
printf (" Scanning PCI bus");
|
||||
debug("0x%08x=0x%08x ", &pex1->pme_msg_det,pex1->pme_msg_det);
|
||||
if (pex1->pme_msg_det) {
|
||||
pex1->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pex1->pme_msg_det);
|
||||
debug (" with errors. Clearing. Now 0x%08x",
|
||||
pex1->pme_msg_det);
|
||||
}
|
||||
debug ("\n");
|
||||
}
|
||||
|
||||
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0x7f;
|
||||
|
||||
@ -88,36 +89,26 @@ pci_mpc86xx_init(struct pci_controller *hose)
|
||||
*/
|
||||
pci_register_hose(hose);
|
||||
|
||||
//#define MPC8548_REV1_PEX12_ERRATA
|
||||
#ifdef MPC8548_REV1_PEX12_ERRATA
|
||||
/* can only read/write 4 bytes */
|
||||
pci_read_config_dword (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®32);
|
||||
printf("pex_mpc85xx_init: pex cr %2x %8x\n",PCI_VENDOR_ID, reg32);
|
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®32);
|
||||
reg32 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg32);
|
||||
#else
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_VENDOR_ID, ®16);
|
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_VENDOR_ID, reg16);
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_DEVICE_ID, ®16);
|
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_DEVICE_ID, reg16);
|
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY \
|
||||
| PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
|
||||
|
||||
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
|
||||
debug("pex_mpc86xx_init: read %2x %4x\n",PCI_COMMAND, reg16);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register.
|
||||
*/
|
||||
// pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
// pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
|
||||
/*
|
||||
* pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
|
||||
* pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
|
||||
*/
|
||||
|
||||
pex1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
|
||||
pex1->powar1 = 0x8004401c; /* 512M MEM space */
|
||||
@ -129,7 +120,6 @@ pci_mpc86xx_init(struct pci_controller *hose)
|
||||
pex1->potar2 = 0x00000000;
|
||||
pex1->potear2 = 0x00000000;
|
||||
|
||||
|
||||
if (!pex1->piwar1) {
|
||||
pex1->pitar1 = 0x00000000;
|
||||
pex1->piwbar1 = (0x80000000 >> 12 ) & 0x000fffff;
|
||||
@ -140,57 +130,34 @@ pci_mpc86xx_init(struct pci_controller *hose)
|
||||
pex1->pitar2 = 0x00000000;
|
||||
pex1->piwbar2 = (0xe2000000 >> 12 ) & 0x000fffff;
|
||||
pex1->piwar2 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
|
||||
|
||||
|
||||
|
||||
/* if (pex1_host) { */
|
||||
/* #ifdef MPC8548_REV1_PEX12_ERRATA */
|
||||
/* pci_write_config_dword (PCI_BDF(0,0,0), 0x18, 0x00ff0100); */
|
||||
/* #else */
|
||||
|
||||
|
||||
* Snoop R/W, 2G */
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80000000;
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n",
|
||||
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_PRIMARY_BUS,0x20);
|
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SECONDARY_BUS,0x00);
|
||||
pci_write_config_byte(PCI_BDF(0,0,0), PCI_SUBORDINATE_BUS,0x1F);
|
||||
/* #endif */
|
||||
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000;
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n",
|
||||
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000;
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n",
|
||||
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
*(u32 *)(0xf8008000)= 0x80200000;
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
|
||||
debug("Received data for addr 0x%08lx is 0x%08lx\n",
|
||||
*(u32*)(0xf8008000), *(u32*)(0xf8008004));
|
||||
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
hose->last_busno = 0x21;
|
||||
debug("pex_mpc86xx_init: last_busno %x\n",hose->last_busno);
|
||||
debug("pex_mpc86xx init: current_busno %x\n ",hose->current_busno);
|
||||
|
||||
|
||||
printf("....PCI scan & enumeration done\n");
|
||||
|
||||
/* *(u32 *)(0xf8008000)= 0x80000000 | (0x12 << 11); */
|
||||
/* printf("Received data for addr 0x%08lx is 0x%08lx\n", *(u32*)(0xf8008000), *(u32*)(0xf8008004)); */
|
||||
|
||||
/* if (hose->last_busno < 1) { */
|
||||
/* hose->last_busno=1; /\*Hack*\/ */
|
||||
/* } else { */
|
||||
/* hose->last_busno = 0; */
|
||||
/* } */
|
||||
/*}*/
|
||||
/* pci_read_config_dword (PCI_BDF(1,0,0), 0x18, ®32); */
|
||||
/* printf("pex_mpc86xx_init: pex cr %2x %8x\n",0x18, reg32); */
|
||||
|
||||
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
@ -947,7 +947,6 @@ spd_sdram(void)
|
||||
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
|
||||
debug("DDR: LARAR1=0x%08x\n", mcm->lawar1);
|
||||
|
||||
|
||||
return memsize * 1024 * 1024;
|
||||
}
|
||||
|
||||
|
||||
@ -33,9 +33,7 @@ unsigned long get_board_sys_clk(ulong dummy);
|
||||
unsigned long get_sysclk_from_px_regs(void);
|
||||
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
void get_sys_info (sys_info_t * sysInfo)
|
||||
void get_sys_info (sys_info_t *sysInfo)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
@ -65,72 +63,77 @@ void get_sys_info (sys_info_t * sysInfo)
|
||||
break;
|
||||
}
|
||||
|
||||
// printf("assigned system bus freq = %d for plat ratio 0x%08lx\n", sysInfo->freqSystemBus, plat_ratio);
|
||||
#if 0
|
||||
printf("assigned system bus freq = %d for plat ratio 0x%08lx\n",
|
||||
sysInfo->freqSystemBus, plat_ratio);
|
||||
#endif
|
||||
|
||||
e600_ratio = (gur->porpllsr) & 0x003f0000;
|
||||
e600_ratio >>= 16;
|
||||
switch(e600_ratio) {
|
||||
|
||||
switch (e600_ratio) {
|
||||
case 0x10:
|
||||
sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
|
||||
sysInfo->freqProcessor = 2 * sysInfo->freqSystemBus;
|
||||
break;
|
||||
case 0x19:
|
||||
sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
|
||||
sysInfo->freqProcessor = 5 * sysInfo->freqSystemBus/2;
|
||||
break;
|
||||
case 0x20:
|
||||
sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
|
||||
sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus;
|
||||
break;
|
||||
case 0x39:
|
||||
sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
|
||||
sysInfo->freqProcessor = 7 * sysInfo->freqSystemBus/2;
|
||||
break;
|
||||
case 0x28:
|
||||
sysInfo->freqProcessor = 4*sysInfo->freqSystemBus;
|
||||
sysInfo->freqProcessor = 4 * sysInfo->freqSystemBus;
|
||||
break;
|
||||
case 0x1d:
|
||||
sysInfo->freqProcessor = 9*sysInfo->freqSystemBus/2;
|
||||
sysInfo->freqProcessor = 9 * sysInfo->freqSystemBus/2;
|
||||
break;
|
||||
default:
|
||||
/* JB - Emulator workaround until real cop is plugged in */
|
||||
/* sysInfo->freqProcessor = 3 * sysInfo->freqSystemBus; */
|
||||
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
|
||||
//sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
|
||||
break;
|
||||
}
|
||||
// printf("assigned processor freq = %d for e600 ratio 0x%08lx\n", sysInfo->freqProcessor, e600_ratio);
|
||||
|
||||
#if 0
|
||||
printf("assigned processor freq = %d for e600 ratio 0x%08lx\n",
|
||||
sysInfo->freqProcessor, e600_ratio);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Measure CPU clock speed (core clock GCLK1, GCLK2)
|
||||
*
|
||||
* (Approx. GCLK frequency in Hz)
|
||||
*/
|
||||
|
||||
int get_clocks (void)
|
||||
int get_clocks(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
sys_info_t sys_info;
|
||||
|
||||
get_sys_info (&sys_info);
|
||||
get_sys_info(&sys_info);
|
||||
gd->cpu_clk = sys_info.freqProcessor;
|
||||
gd->bus_clk = sys_info.freqSystemBus;
|
||||
|
||||
if(gd->cpu_clk != 0) return (0);
|
||||
else return (1);
|
||||
if (gd->cpu_clk != 0)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/********************************************
|
||||
|
||||
/*
|
||||
* get_bus_freq
|
||||
* return system bus freq in Hz
|
||||
*********************************************/
|
||||
ulong get_bus_freq (ulong dummy)
|
||||
* Return system bus freq in Hz
|
||||
*/
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
ulong val;
|
||||
|
||||
sys_info_t sys_info;
|
||||
|
||||
get_sys_info (&sys_info);
|
||||
get_sys_info(&sys_info);
|
||||
val = sys_info.freqSystemBus;
|
||||
|
||||
return val;
|
||||
@ -139,85 +142,74 @@ ulong get_bus_freq (ulong dummy)
|
||||
unsigned long get_sysclk_from_px_regs()
|
||||
{
|
||||
ulong val;
|
||||
u8 vclkh,vclkl;
|
||||
u8 vclkh, vclkl;
|
||||
|
||||
vclkh = in8(PIXIS_BASE+PIXIS_VCLKH);
|
||||
vclkl = in8(PIXIS_BASE+PIXIS_VCLKL);
|
||||
vclkh = in8(PIXIS_BASE + PIXIS_VCLKH);
|
||||
vclkl = in8(PIXIS_BASE + PIXIS_VCLKL);
|
||||
|
||||
if((vclkh == 0x84) && (vclkl ==0x07))
|
||||
{
|
||||
if ((vclkh == 0x84) && (vclkl == 0x07)) {
|
||||
val = 33000000;
|
||||
}
|
||||
if((vclkh == 0x3F) && (vclkl ==0x20))
|
||||
{
|
||||
if ((vclkh == 0x3F) && (vclkl == 0x20)) {
|
||||
val = 40000000;
|
||||
}
|
||||
if((vclkh == 0x3F) && (vclkl ==0x2A))
|
||||
{
|
||||
if ((vclkh == 0x3F) && (vclkl == 0x2A)) {
|
||||
val = 50000000;
|
||||
}
|
||||
if((vclkh == 0x24) && (vclkl ==0x04))
|
||||
{
|
||||
if ((vclkh == 0x24) && (vclkl == 0x04)) {
|
||||
val = 66000000;
|
||||
}
|
||||
if((vclkh == 0x3F) && (vclkl ==0x4B))
|
||||
{
|
||||
if ((vclkh == 0x3F) && (vclkl == 0x4B)) {
|
||||
val = 83000000;
|
||||
}
|
||||
if((vclkh == 0x3F) && (vclkl ==0x5C))
|
||||
{
|
||||
if ((vclkh == 0x3F) && (vclkl == 0x5C)) {
|
||||
val = 100000000;
|
||||
}
|
||||
if((vclkh == 0xDF) && (vclkl ==0x3B))
|
||||
{
|
||||
if ((vclkh == 0xDF) && (vclkl == 0x3B)) {
|
||||
val = 134000000;
|
||||
}
|
||||
if((vclkh == 0xDF) && (vclkl ==0x4B))
|
||||
{
|
||||
if ((vclkh == 0xDF) && (vclkl == 0x4B)) {
|
||||
val = 166000000;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/******* From MPC8641HPCN Design Workbook ************
|
||||
*
|
||||
|
||||
/*
|
||||
* get_board_sys_clk
|
||||
* reads the FPGA on board for CONFIG_SYS_CLK_FREQ
|
||||
*
|
||||
********************************************************/
|
||||
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
|
||||
*/
|
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy)
|
||||
{
|
||||
u8 i, go_bit, rd_clks;
|
||||
ulong val;
|
||||
|
||||
go_bit = in8(PIXIS_BASE+PIXIS_VCTL);
|
||||
go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
|
||||
go_bit &= 0x01;
|
||||
|
||||
rd_clks = in8(PIXIS_BASE+PIXIS_VCFGEN0);
|
||||
rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
|
||||
rd_clks &= 0x1C;
|
||||
|
||||
/* Only if both go bit and the SCLK bit in VCFGEN0 are set
|
||||
/*
|
||||
* Only if both go bit and the SCLK bit in VCFGEN0 are set
|
||||
* should we be using the AUX register. Remember, we also set the
|
||||
* GO bit to boot from the alternate bank on the on-board flash
|
||||
*/
|
||||
|
||||
if(go_bit)
|
||||
{
|
||||
if(rd_clks == 0x1c)
|
||||
i = in8(PIXIS_BASE+PIXIS_AUX);
|
||||
if (go_bit) {
|
||||
if (rd_clks == 0x1c)
|
||||
i = in8(PIXIS_BASE + PIXIS_AUX);
|
||||
else
|
||||
i = in8(PIXIS_BASE+PIXIS_SPD);
|
||||
//val = get_sysclk_from_px_regs();
|
||||
i = in8(PIXIS_BASE + PIXIS_SPD);
|
||||
} else {
|
||||
i = in8(PIXIS_BASE + PIXIS_SPD);
|
||||
}
|
||||
else
|
||||
i = in8(PIXIS_BASE+PIXIS_SPD);
|
||||
|
||||
i &= 0x07;
|
||||
|
||||
switch(i)
|
||||
{
|
||||
switch (i) {
|
||||
case 0:
|
||||
val = 33000000;
|
||||
break;
|
||||
|
||||
@ -783,12 +783,12 @@ ppcDcbz:
|
||||
dcbz r0,r3
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/*-------------------------------------------------------------------------- */
|
||||
/* Function: ppcSync */
|
||||
/* Description: Processor Synchronize */
|
||||
/* Input: none. */
|
||||
/* Output: none. */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/*-------------------------------------------------------------------------- */
|
||||
.globl ppcSync
|
||||
ppcSync:
|
||||
sync
|
||||
|
||||
@ -1,6 +1,4 @@
|
||||
/*
|
||||
* linux/arch/ppc/kernel/traps.c
|
||||
*
|
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
||||
*
|
||||
* Modified by Cort Dougan (cort@cs.nmt.edu)
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2006 Freescale Semiconductor.
|
||||
*
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
@ -22,8 +23,7 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* mpc8641hpc3 board configuration file
|
||||
*
|
||||
* MPC8641HPCN board configuration file
|
||||
*
|
||||
* Make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
|
||||
@ -40,46 +40,36 @@
|
||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
|
||||
#undef DEBUG
|
||||
|
||||
//#define RUN_DIAG 1
|
||||
#ifdef RUN_DIAG
|
||||
#define CFG_DIAG_ADDR 0xff800000
|
||||
#endif
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xfff00100
|
||||
|
||||
//#define CONFIG_PCI
|
||||
#undef CONFIG_PCI
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
/*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */
|
||||
/*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */
|
||||
|
||||
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
|
||||
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
|
||||
#define CONFIG_ALTIVEC 1
|
||||
/*-----------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
* L2CR setup -- make sure this is right for your board!
|
||||
*/
|
||||
|
||||
#define CFG_L2
|
||||
#define L2_INIT 0
|
||||
#define L2_ENABLE (L2CR_L2E)
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
//#define CONFIG_SYS_CLK_FREQ 33000000
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
/* JB - XXX - Are these available on 86xx? */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
@ -143,20 +133,12 @@
|
||||
#define CFG_DDR_CS3_BNDS 0x00000FFF //Not done
|
||||
#define CFG_DDR_CS4_BNDS 0x00000FFF //Not done
|
||||
#define CFG_DDR_CS5_BNDS 0x00000FFF //Not done
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus
|
||||
*/
|
||||
//#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
|
||||
//#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
|
||||
|
||||
/* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
|
||||
* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000
|
||||
* We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff
|
||||
* map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff.
|
||||
* However, when u-boot comes up, the flash_init needs hard start addresses
|
||||
@ -165,15 +147,12 @@
|
||||
* knows where the flash is and the user can download u-boot code from promjet to
|
||||
* fef00000 <- more intuitive than fe700000. Note that, on switching the boot
|
||||
* location, fef00000 becomes fff00000.
|
||||
*/
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */
|
||||
#define CFG_FLASH_BASE2 0xff800000
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
|
||||
|
||||
|
||||
/*Sri: This looks like a good place to init all the Local Bus chip selects*/
|
||||
|
||||
#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */
|
||||
#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/
|
||||
|
||||
@ -186,11 +165,12 @@
|
||||
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
|
||||
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
|
||||
|
||||
#define PIXIS_BASE 0xf8100000 /* PIXIS registers*/
|
||||
#define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/
|
||||
#define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/
|
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/
|
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register*/
|
||||
|
||||
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
|
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */
|
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
|
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
|
||||
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
|
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
|
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */
|
||||
@ -202,9 +182,7 @@
|
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
|
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
|
||||
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
//#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
@ -212,11 +190,9 @@
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
/*#define CFG_HPCN_FLASH_CFI_DRIVER */
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
@ -265,7 +241,9 @@
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
/*
|
||||
* Pass open firmware flat tree to kernel
|
||||
*/
|
||||
#define CONFIG_OF_FLAT_TREE 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
@ -297,13 +275,10 @@
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
//#define CFG_PCI1_MEM_BASE 0xd0000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
//#define CFG_PCI1_IO_BASE 0xe0000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
//#define CFG_PCI1_IO_BUS 0x00000000
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
/* For RTL8139 */
|
||||
@ -316,29 +291,18 @@
|
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
|
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
// #define CFG_PCI1_MEM_BASE 0x80000000
|
||||
// #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
// #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
// #define CFG_PCI1_IO_BASE 0xe2000000
|
||||
// #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
// #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
//#define CFG_SCSI_SCAN_BUS_REVERSE
|
||||
|
||||
#undef CFG_SCSI_SCAN_BUS_REVERSE
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_RTL8139
|
||||
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
@ -349,7 +313,6 @@
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
//#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
@ -371,7 +334,6 @@
|
||||
#define CONFIG_MPC86XX_TSEC4 1
|
||||
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
|
||||
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC3_PHY_ADDR 2
|
||||
@ -389,12 +351,10 @@
|
||||
/* BAT0 2G Cacheable, non-guarded
|
||||
* 0x0000_0000 2G DDR
|
||||
*/
|
||||
//#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE)
|
||||
#define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP)
|
||||
//#define CFG_IBAT0L CFG_DBAT0L
|
||||
//#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
|
||||
#define CFG_DBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE )
|
||||
#define CFG_DBAT0U ( BATU_BL_512M | BATU_VS | BATU_VP )
|
||||
#define CFG_IBAT0L ( BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT0U CFG_DBAT0U
|
||||
|
||||
/* BAT1 1G Cache-inhibited, guarded
|
||||
@ -402,7 +362,8 @@
|
||||
* 0xa000_0000 512M PCI-Express 2 Memory
|
||||
** SS - Changed it for operating from 0xd0000000
|
||||
*/
|
||||
#define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT1U CFG_DBAT1U
|
||||
@ -410,7 +371,8 @@
|
||||
/* BAT2 512M Cache-inhibited, guarded
|
||||
* 0xc000_0000 512M RapidIO Memory
|
||||
*/
|
||||
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
|
||||
#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT2U CFG_DBAT2U
|
||||
@ -418,7 +380,8 @@
|
||||
/* BAT3 4M Cache-inhibited, guarded
|
||||
* 0xf800_0000 4M CCSR
|
||||
*/
|
||||
#define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
|
||||
#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT3U CFG_DBAT3U
|
||||
@ -428,7 +391,8 @@
|
||||
* 0xe300_0000 16M PCI-Express 2 I/0
|
||||
** SS - Note that this is at 0xe0000000
|
||||
*/
|
||||
#define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
||||
#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT4U CFG_DBAT4U
|
||||
@ -444,12 +408,12 @@
|
||||
/* BAT6 32M Cache-inhibited, guarded
|
||||
* 0xfe00_0000 32M FLASH
|
||||
*/
|
||||
#define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT6L ( CFG_FLASH_BASE | BATL_PP_RW \
|
||||
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
||||
#define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT6U CFG_DBAT6U
|
||||
|
||||
|
||||
#define CFG_DBAT7L 0x00000000
|
||||
#define CFG_DBAT7U 0x00000000
|
||||
#define CFG_IBAT7L 0x00000000
|
||||
@ -461,17 +425,17 @@
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
@ -582,11 +546,12 @@
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
|
||||
#define CONFIG_SERVERIP 10.82.193.104
|
||||
#define CONFIG_GATEWAYIP 10.82.193.254
|
||||
#define CONFIG_NETMASK 255.255.252.0
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 10.82.193.104
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
|
||||
#define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
@ -599,7 +564,7 @@
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=400000\0" \
|
||||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||
"pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \
|
||||
"pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0"\
|
||||
"pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \
|
||||
"pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \
|
||||
"pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2006 Freescale Semiconductor.
|
||||
* Jeffrey Brown (jeffrey@freescale.com)
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*/
|
||||
@ -9,7 +9,7 @@
|
||||
|
||||
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
|
||||
|
||||
/*----------------------------------------------------------------
|
||||
/*
|
||||
* l2cr values. Look in config_<BOARD>.h for the actual setup
|
||||
*/
|
||||
#define l2cr 1017
|
||||
@ -23,7 +23,7 @@
|
||||
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
|
||||
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
|
||||
|
||||
/*----------------------------------------------------------------
|
||||
/*
|
||||
* BAT settings. Look in config_<BOARD>.h for the actual setup
|
||||
*/
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user