mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-09 12:13:00 -04:00
Moved board specific values in config file
The lowlevel_init file contained some hard-coded values to setup the RAM. These board related values are moved into the board configuration file. Signed-off-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
2720178533
commit
5e1fe88fe3
@ -158,6 +158,7 @@
|
|||||||
/* Switch peripheral to PLL 3 */
|
/* Switch peripheral to PLL 3 */
|
||||||
ldr r0, =CCM_BASE_ADDR
|
ldr r0, =CCM_BASE_ADDR
|
||||||
ldr r1, =0x000010C0
|
ldr r1, =0x000010C0
|
||||||
|
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
|
||||||
str r1, [r0, #CLKCTL_CBCMR]
|
str r1, [r0, #CLKCTL_CBCMR]
|
||||||
ldr r1, =0x13239145
|
ldr r1, =0x13239145
|
||||||
str r1, [r0, #CLKCTL_CBCDR]
|
str r1, [r0, #CLKCTL_CBCDR]
|
||||||
@ -171,6 +172,7 @@
|
|||||||
ldr r1, =0x19239145
|
ldr r1, =0x19239145
|
||||||
str r1, [r0, #CLKCTL_CBCDR]
|
str r1, [r0, #CLKCTL_CBCDR]
|
||||||
ldr r1, =0x000020C0
|
ldr r1, =0x000020C0
|
||||||
|
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
|
||||||
str r1, [r0, #CLKCTL_CBCMR]
|
str r1, [r0, #CLKCTL_CBCMR]
|
||||||
|
|
||||||
mov r3, #DP_OP_216
|
mov r3, #DP_OP_216
|
||||||
@ -201,9 +203,10 @@
|
|||||||
/* setup the rest */
|
/* setup the rest */
|
||||||
/* Use lp_apm (24MHz) source for perclk */
|
/* Use lp_apm (24MHz) source for perclk */
|
||||||
ldr r1, =0x000020C2
|
ldr r1, =0x000020C2
|
||||||
|
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
|
||||||
str r1, [r0, #CLKCTL_CBCMR]
|
str r1, [r0, #CLKCTL_CBCMR]
|
||||||
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
|
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
|
||||||
ldr r1, =0x59E35100
|
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
|
||||||
str r1, [r0, #CLKCTL_CBCDR]
|
str r1, [r0, #CLKCTL_CBCDR]
|
||||||
|
|
||||||
/* Restore the default values in the Gate registers */
|
/* Restore the default values in the Gate registers */
|
||||||
|
@ -160,6 +160,9 @@
|
|||||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||||
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_DDR_CLKSEL 0
|
||||||
|
#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
* FLASH and environment organization
|
* FLASH and environment organization
|
||||||
*/
|
*/
|
||||||
|
Loading…
x
Reference in New Issue
Block a user