diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 0c199cdab..4d92c53b9 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,10 +26,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#endif
-
 /* exynos4: return pll clock frequency */
 static unsigned long exynos4_get_pll_clk(int pllreg)
 {
@@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
 	/* SDIV [2:0] */
 	s = r & 0x7;
 
-	freq = CONFIG_SYS_CLK_FREQ_C210;
+	freq = CONFIG_SYS_CLK_FREQ;
 
 	if (pllreg == EPLL) {
 		k = k & 0xffff;
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index be000cbaf..8286680f2 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210	24000000
+#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
diff --git a/include/configs/trats.h b/include/configs/trats.h
index acb324153..10f11d957 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210	24000000
+#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG