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x86: Fix MMCR Access

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Change sc520 MMCR Access to use memory accessor functions

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This commit is contained in:
Graeme Russ 2010-04-24 00:05:37 +10:00 committed by Wolfgang Denk
parent 535ad2db06
commit 64a0a4995e
5 changed files with 103 additions and 92 deletions
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33
arch/i386/cpu/sc520/sc520.c
View File

@ -44,24 +44,24 @@ void init_sc520(void)
/* Set the UARTxCTL register at it's slower, /* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference * baud clock giving us a 1.8432 MHz reference
*/ */
sc520_mmcr->uart1ctl = 0x07; writeb(0x07, &sc520_mmcr->uart1ctl);
sc520_mmcr->uart2ctl = 0x07; writeb(0x07, &sc520_mmcr->uart2ctl);
/* first set the timer pin mapping */ /* first set the timer pin mapping */
sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */ writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
/* enable PCI bus arbitrer */ /* enable PCI bus arbitrer */
sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */ writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */
sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */ writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */
sc520_mmcr->hbctl = 0x04; /* enable posted-writes */ writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */
if (CONFIG_SYS_SC520_HIGH_SPEED) { if (CONFIG_SYS_SC520_HIGH_SPEED) {
sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */ writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */
gd->cpu_clk = 133000000; gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n"); printf("## CPU Speed set to 133MHz\n");
} else { } else {
sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */ writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */
printf("## CPU Speed set to 100MHz\n"); printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000; gd->cpu_clk = 100000000;
} }
@ -74,7 +74,7 @@ void init_sc520(void)
"loop 0b\n": : : "ecx"); "loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */ /* turn on the SDRAM write buffer */
sc520_mmcr->dbctl = 0x11; writeb(0x11, &sc520_mmcr->dbctl);
/* turn on the cache and disable write through */ /* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n" asm("movl %%cr0, %%eax\n"
@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0; u32 dram_present=0;
u32 dram_ctrl; u32 dram_ctrl;
#ifdef CONFIG_SYS_SDRAM_DRCTMCTL #ifdef CONFIG_SYS_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part, /* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here, * in sc520_asm.S, during 'mem_init'. If we muck with them here,
@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void)
* simply dictates it. * simply dictates it.
*/ */
#else #else
int val; u8 tmp;
u8 val;
int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void)
val = 3; /* 62.4us */ val = 3; /* 62.4us */
} }
sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4); tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
writeb(tmp, &sc520_mmcr->drcctl);
val = sc520_mmcr->drctmctl & 0xf0; val = readb(&sc520_mmcr->drctmctl) & 0xf0;
if (cas_precharge_delay==3) { if (cas_precharge_delay==3) {
val |= 0x04; /* 3T */ val |= 0x04; /* 3T */
@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void)
} else { } else {
val |= 1; val |= 1;
} }
sc520_mmcr->drctmctl = val; writeb(val, &c520_mmcr->drctmctl);
#endif #endif
/* We read-back the configuration of the dram /* We read-back the configuration of the dram
* controller that the assembly code wrote */ * controller that the assembly code wrote */
dram_ctrl = sc520_mmcr->drcbendadr; dram_ctrl = readl(&sc520_mmcr->drcbendadr);
bd->bi_dram[0].start = 0; bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) { if (dram_ctrl & 0x80) {
@ -191,7 +194,7 @@ void reset_cpu(ulong addr)
{ {
printf("Resetting using SC520 MMCR\n"); printf("Resetting using SC520 MMCR\n");
/* Write a '1' to the SYS_RST of the RESCFG MMCR */ /* Write a '1' to the SYS_RST of the RESCFG MMCR */
sc520_mmcr->rescfg = 0x01; writeb(0x01, &sc520_mmcr->rescfg);
/* NOTREACHED */ /* NOTREACHED */
} }

24
arch/i386/cpu/sc520/sc520_pci.c
View File

@ -25,6 +25,7 @@
#include <common.h> #include <common.h>
#include <pci.h> #include <pci.h>
#include <asm/io.h>
#include <asm/pci.h> #include <asm/pci.h>
#include <asm/ic/sc520.h> #include <asm/ic/sc520.h>
@ -63,6 +64,8 @@ int sc520_pci_ints[15] = {
int pci_sc520_set_irq(int pci_pin, int irq) int pci_sc520_set_irq(int pci_pin, int irq)
{ {
int i; int i;
u8 tmpb;
u16 tmpw;
# if 1 # if 1
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
@ -80,31 +83,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
/* PCI interrupt mapping (A through D)*/ /* PCI interrupt mapping (A through D)*/
for (i=0; i<=3 ;i++) { for (i=0; i<=3 ;i++) {
if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority) if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED; writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
} }
/* GP IRQ interrupt mapping */ /* GP IRQ interrupt mapping */
for (i=0; i<=10 ;i++) { for (i=0; i<=10 ;i++) {
if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority) if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED; writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
} }
/* Set the trigger to level */ /* Set the trigger to level */
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] = tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit; tmpb |= sc520_irq[irq].level_bit;
writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
if (pci_pin < 4) { if (pci_pin < 4) {
/* PCI INTA-INTD */ /* PCI INTA-INTD */
/* route the interrupt */ /* route the interrupt */
sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority; writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
} else { } else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */ /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority; writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
/* also set the polarity in this case */ /* also set the polarity in this case */
sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4)); tmpw = readw(&sc520_mmcr->intpinpol);
tmpw |= (1 << (pci_pin-4));
writew(tmpw, &sc520_mmcr->intpinpol);
} }
/* register the pin */ /* register the pin */

27
arch/i386/cpu/sc520/sc520_ssi.c
View File

@ -24,6 +24,7 @@
/* stuff specific for the sc520, but independent of implementation */ /* stuff specific for the sc520, but independent of implementation */
#include <common.h> #include <common.h>
#include <asm/io.h>
#include <asm/ic/ssi.h> #include <asm/ic/ssi.h>
#include <asm/ic/sc520.h> #include <asm/ic/sc520.h>
@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
temp |= PHS_INV_ENB; temp |= PHS_INV_ENB;
} }
sc520_mmcr->ssictl = temp; writeb(temp, &sc520_mmcr->ssictl);
return 0; return 0;
} }
u8 ssi_txrx_byte(u8 data) u8 ssi_txrx_byte(u8 data)
{ {
sc520_mmcr->ssixmit = data; writeb(data, &sc520_mmcr->ssixmit);
while (sc520_mmcr->ssista & SSISTA_BSY); while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV; writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
while (sc520_mmcr->ssista & SSISTA_BSY); while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
return sc520_mmcr->ssircv; return readb(&sc520_mmcr->ssircv);
} }
void ssi_tx_byte(u8 data) void ssi_tx_byte(u8 data)
{ {
sc520_mmcr->ssixmit = data; writeb(data, &sc520_mmcr->ssixmit);
while (sc520_mmcr->ssista & SSISTA_BSY); while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT; writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
} }
u8 ssi_rx_byte(void) u8 ssi_rx_byte(void)
{ {
while (sc520_mmcr->ssista & SSISTA_BSY); while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV; writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
while (sc520_mmcr->ssista & SSISTA_BSY); while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
return sc520_mmcr->ssircv; return readb(&sc520_mmcr->ssircv);
} }

31
arch/i386/cpu/sc520/sc520_timer.c
View File

@ -24,13 +24,14 @@
/* stuff specific for the sc520, but independent of implementation */ /* stuff specific for the sc520, but independent of implementation */
#include <common.h> #include <common.h>
#include <asm/io.h>
#include <asm/interrupt.h> #include <asm/interrupt.h>
#include <asm/ic/sc520.h> #include <asm/ic/sc520.h>
void sc520_timer_isr(void) void sc520_timer_isr(void)
{ {
/* Ack the GP Timer Interrupt */ /* Ack the GP Timer Interrupt */
sc520_mmcr->gptmrsta = 0x02; writeb(0x02, &sc520_mmcr->gptmrsta);
} }
int timer_init(void) int timer_init(void)
@ -42,28 +43,28 @@ int timer_init(void)
irq_install_handler (0, timer_isr, NULL); irq_install_handler (0, timer_isr, NULL);
/* Map GP Timer 1 to Master PIC IR0 */ /* Map GP Timer 1 to Master PIC IR0 */
sc520_mmcr->gp_tmr_int_map[1] = 0x01; writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
/* Disable GP Timers 1 & 2 - Allow configuration writes */ /* Disable GP Timers 1 & 2 - Allow configuration writes */
sc520_mmcr->gptmr1ctl = 0x4000; writew(0x4000, &sc520_mmcr->gptmr1ctl);
sc520_mmcr->gptmr2ctl = 0x4000; writew(0x4000, &sc520_mmcr->gptmr2ctl);
/* Reset GP Timers 1 & 2 */ /* Reset GP Timers 1 & 2 */
sc520_mmcr->gptmr1cnt = 0x0000; writew(0x0000, &sc520_mmcr->gptmr1cnt);
sc520_mmcr->gptmr2cnt = 0x0000; writew(0x0000, &sc520_mmcr->gptmr2cnt);
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */ /* Setup GP Timer 2 as a 100kHz (10us) prescaler */
sc520_mmcr->gptmr2maxcmpa = 83; writew(83, &sc520_mmcr->gptmr2maxcmpa);
sc520_mmcr->gptmr2ctl = 0xc001; writew(0xc001, &sc520_mmcr->gptmr2ctl);
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */ /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
sc520_mmcr->gptmr1maxcmpa = 100; writew(100, &sc520_mmcr->gptmr1maxcmpa);
sc520_mmcr->gptmr1ctl = 0xe009; writew(0xe009, &sc520_mmcr->gptmr1ctl);
unmask_irq (0); unmask_irq (0);
/* Clear the GP Timer 1 status register to get the show rolling*/ /* Clear the GP Timer 1 status register to get the show rolling*/
sc520_mmcr->gptmrsta = 0x02; writeb(0x02, &sc520_mmcr->gptmrsta);
return 0; return 0;
} }
@ -74,11 +75,11 @@ void __udelay(unsigned long usec)
long u; long u;
long temp; long temp;
temp = sc520_mmcr->swtmrmilli; temp = readw(&sc520_mmcr->swtmrmilli);
temp = sc520_mmcr->swtmrmicro; temp = readw(&sc520_mmcr->swtmrmicro);
do { do {
m += sc520_mmcr->swtmrmilli; m += readw(&sc520_mmcr->swtmrmilli);
u = sc520_mmcr->swtmrmicro + (m * 1000); u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
} while (u < usec); } while (u < usec);
} }

80
board/eNET/eNET.c
View File

@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void init_sc520_enet (void) void init_sc520_enet (void)
{ {
/* Set CPU Speed to 100MHz */ /* Set CPU Speed to 100MHz */
sc520_mmcr->cpuctl = 0x01; writeb(0x01, &sc520_mmcr->cpuctl);
/* wait at least one millisecond */ /* wait at least one millisecond */
asm("movl $0x2000,%%ecx\n" asm("movl $0x2000,%%ecx\n"
@ -55,7 +55,7 @@ void init_sc520_enet (void)
"loop 0b\n": : : "ecx"); "loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */ /* turn on the SDRAM write buffer */
sc520_mmcr->dbctl = 0x11; writeb(0x11, &sc520_mmcr->dbctl);
/* turn on the cache and disable write through */ /* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n" asm("movl %%cr0, %%eax\n"
@ -70,51 +70,51 @@ int board_early_init_f(void)
{ {
init_sc520_enet(); init_sc520_enet();
sc520_mmcr->gpcsrt = 0x01; /* GP Chip Select Recovery Time */ writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
sc520_mmcr->gpcspw = 0x07; /* GP Chip Select Pulse Width */ writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
sc520_mmcr->gpcsoff = 0x00; /* GP Chip Select Offset */ writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
sc520_mmcr->gprdw = 0x05; /* GP Read pulse width */ writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
sc520_mmcr->gprdoff = 0x01; /* GP Read offset */ writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */ writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
sc520_mmcr->gpwroff = 0x01; /* GP Write offset */ writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */ writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */ writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */ writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */ writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */ writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */ writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */ writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */ writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */ writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */ writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
sc520_mmcr->par[5] = 0x340710f8; /* Uart D (GPCS5, 0x010f8, 8 Bytes) */ writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
sc520_mmcr->par[6] = 0xe3ffc000; /* SDRAM (0x00000000, 128MB) */ writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
sc520_mmcr->par[7] = 0xaa3fd000; /* StrataFlash (ROMCS1, 0x10000000, 16MB) */ writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
sc520_mmcr->par[8] = 0xca3fd100; /* StrataFlash (ROMCS2, 0x11000000, 16MB) */ writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
sc520_mmcr->par[9] = 0x4203d900; /* SRAM (GPCS0, 0x19000000, 1MB) */ writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
sc520_mmcr->par[10] = 0x4e03d910; /* SRAM (GPCS3, 0x19100000, 1MB) */ writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
sc520_mmcr->par[11] = 0x50018100; /* DP-RAM (GPCS4, 0x18100000, 4kB) */ writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
sc520_mmcr->par[12] = 0x54020000; /* CFLASH1 (0x200000000, 4kB) */ writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
sc520_mmcr->par[13] = 0x5c020001; /* CFLASH2 (0x200010000, 4kB) */ writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */ /* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */ /* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */ /* Disable Watchdog */
sc520_mmcr->wdtmrctl = 0x3333; writew(0x3333, &sc520_mmcr->wdtmrctl);
sc520_mmcr->wdtmrctl = 0xcccc; writew(0xcccc, &sc520_mmcr->wdtmrctl);
sc520_mmcr->wdtmrctl = 0x0000; writew(0x0000, &sc520_mmcr->wdtmrctl);
/* Chip Select Configuration */ /* Chip Select Configuration */
sc520_mmcr->bootcsctl = 0x0033; writew(0x0033, &sc520_mmcr->bootcsctl);
sc520_mmcr->romcs1ctl = 0x0615; writew(0x0615, &sc520_mmcr->romcs1ctl);
sc520_mmcr->romcs2ctl = 0x0615; writew(0x0615, &sc520_mmcr->romcs2ctl);
sc520_mmcr->adddecctl = 0x02; writeb(0x02, &sc520_mmcr->adddecctl);
sc520_mmcr->uart1ctl = 0x07; writeb(0x07, &sc520_mmcr->uart1ctl);
sc520_mmcr->sysarbctl = 0x06; writeb(0x06, &sc520_mmcr->sysarbctl);
sc520_mmcr->sysarbmenb = 0x0003; writew(0x0003, &sc520_mmcr->sysarbmenb);
return 0; return 0;
} }