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ppc4xx: Correct 405EX PCIe UTL register mapping

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Map 4k mem space for UTL registers for each port.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-11-18 14:44:44 +01:00
parent 9ea61b5796
commit 653811a3c2
1 changed files with 3 additions and 3 deletions
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6
cpu/ppc4xx/4xx_pcie.c
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@ -412,14 +412,14 @@ static void ppc4xx_setup_utl(u32 port)
case 0: case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
break; break;
case 1: case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
break; break;
@ -554,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
#endif /* CONFIG_405EX */ #endif /* CONFIG_405EX */
int ppc4xx_init_pcie_port_hw(int port, int rootport) int ppc4xx_init_pcie_port_hw(int port, int rootport)
__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
/* /*
* We map PCI Express configuration access into the 512MB regions * We map PCI Express configuration access into the 512MB regions