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SPC1920: cleanup memory contoller setup

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This commit is contained in:
Markus Klotzbuecher 2007-01-09 16:02:48 +01:00 committed by Markus Klotzbuecher
parent 8fc2102faa
commit 67fea022fa
3 changed files with 10 additions and 15 deletions
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4
board/spc1920/hpi.c
View File

@ -148,8 +148,8 @@ int hpi_init(void)
udelay(100); udelay(100);
memctl->memc_mamr = CFG_MAMR; memctl->memc_mamr = CFG_MAMR;
memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_or3 = CFG_OR3;
memctl->memc_br3 = CFG_BR3_PRELIM; memctl->memc_br3 = CFG_BR3;
/* reset dsp */ /* reset dsp */
dsp_reset(); dsp_reset();

11
board/spc1920/spc1920.c
View File

@ -175,14 +175,9 @@ long int initdram (int board_type)
/* initalize the DSP Host Port Interface */ /* initalize the DSP Host Port Interface */
hpi_init(); hpi_init();
/* PLD Setup */ /* FRAM Setup */
memctl->memc_or4 = CFG_OR4_PRELIM; memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4_PRELIM; memctl->memc_br4 = CFG_BR4;
udelay(1000);
/* PLD Setup */
memctl->memc_or5 = CFG_OR5_PRELIM;
memctl->memc_br5 = CFG_BR5_PRELIM;
udelay(1000); udelay(1000);
return (size_b0); return (size_b0);

10
include/configs/spc1920.h
View File

@ -361,14 +361,14 @@
* DSP Host Port Interface CS3 * DSP Host Port Interface CS3
*/ */
#define CFG_SPC1920_HPI_BASE 0x90000000 #define CFG_SPC1920_HPI_BASE 0x90000000
#define CFG_PRELIM_OR3_AM 0xF0000000 #define CFG_PRELIM_OR3_AM 0xF8000000
#define CFG_OR3_PRELIM (CFG_PRELIM_OR3_AM | \ #define CFG_OR3 (CFG_PRELIM_OR3_AM | \
OR_G5LS | \ OR_G5LS | \
OR_SCY_0_CLK | \ OR_SCY_0_CLK | \
OR_BI) OR_BI)
#define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
BR_MS_UPMA | \ BR_MS_UPMA | \
BR_PS_16 | \ BR_PS_16 | \
BR_V); BR_V);
@ -396,13 +396,13 @@
*/ */
#define CFG_SPC1920_FRAM_BASE 0x80100000 #define CFG_SPC1920_FRAM_BASE 0x80100000
#define CFG_PRELIM_OR4_AM 0xffff8000 #define CFG_PRELIM_OR4_AM 0xffff8000
#define CFG_OR4_PRELIM (CFG_PRELIM_OR4_AM | \ #define CFG_OR4 (CFG_PRELIM_OR4_AM | \
OR_ACS_DIV2 | \ OR_ACS_DIV2 | \
OR_BI | \ OR_BI | \
OR_SCY_4_CLK | \ OR_SCY_4_CLK | \
OR_TRLX) OR_TRLX)
#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); #define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* /*
* PLD CS5 * PLD CS5