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mpc83xx: cosmetic: MPC8315ERDB.h checkpatch compliance

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:11 -05:00 committed by Kim Phillips
parent 261c07bc67
commit 6f681b7349
1 changed files with 145 additions and 108 deletions
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163
include/configs/MPC8315ERDB.h
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@ -128,11 +128,11 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \ | DDRCDR_PZ_LOZ \
| DDRCDR_NZ_LOZ \ | DDRCDR_NZ_LOZ \
| DDRCDR_ODT \ | DDRCDR_ODT \
| DDRCDR_Q_DRN ) | DDRCDR_Q_DRN)
/* 0x7b880001 */ /* 0x7b880001 */
/* /*
* Manually set up DDR parameters * Manually set up DDR parameters
@ -140,47 +140,48 @@
*/ */
#define CONFIG_SYS_DDR_SIZE 128 /* MB */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \ | 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) | CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
/* 0x80010102 */ /* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | (0 << TIMING_CFG0_WRT_SHIFT) \
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | (0 << TIMING_CFG0_RRT_SHIFT) \
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | (0 << TIMING_CFG0_WWT_SHIFT) \
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00220802 */ /* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
| ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ | (6 << TIMING_CFG1_REFREC_SHIFT) \
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | (2 << TIMING_CFG1_WRREC_SHIFT) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x27256222 */ /* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \ | (4 << TIMING_CFG2_CPO_SHIFT) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x121048c5 */ /* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03600100 */ /* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE ) | SDRAM_CFG_32_BE)
/* 0x43080000 */ /* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) | (0x0232 << SDRAM_MODE_SD_SHIFT))
/* ODT 150ohm CL=3, AL=1 on SDRAM */ /* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000 #define CONFIG_SYS_DDR_MODE2 0x00000000
@ -203,7 +204,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* /*
* Local Bus Configuration & Clock Setup * Local Bus Configuration & Clock Setup
@ -224,12 +226,13 @@
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ /* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
| BR_V ) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ #define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \ | OR_UPM_XAM \
| OR_GPCM_CSNT \ | OR_GPCM_CSNT \
@ -238,10 +241,11 @@
| OR_GPCM_SCY_15 \ | OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \ | OR_GPCM_TRLX \
| OR_GPCM_EHTR \ | OR_GPCM_EHTR \
| OR_GPCM_EAD ) | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ /* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#undef CONFIG_SYS_FLASH_CHECKSUM #undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@ -278,16 +282,16 @@
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \ | OR_FCM_CSCT \
| OR_FCM_CST \ | OR_FCM_CST \
| OR_FCM_CHT \ | OR_FCM_CHT \
| OR_FCM_SCY_1 \ | OR_FCM_SCY_1 \
| OR_FCM_TRLX \ | OR_FCM_TRLX \
| OR_FCM_EHTR ) | OR_FCM_EHTR)
/* 0xFFFF8396 */ /* 0xFFFF8396 */
#ifdef CONFIG_NAND_U_BOOT #ifdef CONFIG_NAND_U_BOOT
@ -344,7 +348,7 @@
/* I2C */ /* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C #define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
#define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_OFFSET 0x3000
@ -482,7 +486,8 @@
CONFIG_ENV_RANGE) CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT) #elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SIZE 0x2000
#else #else
@ -537,9 +542,11 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ /* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/* /*
@ -564,42 +571,71 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */ /* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_128M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
| BATU_BL_8M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ /* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ | BATL_PP_10 \
BATU_VS | BATU_VP) | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* Stack in dcache: cacheable, no memory coherence */ /* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* PCI MEM space: cacheable */ /* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* PCI MMIO space: cache-inhibit and guarded */ /* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
@ -649,7 +685,8 @@
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \ "tftp $fdtaddr $fdtfile;" \