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Fix two bugs for MPC83xx DDR2 controller SPD Init

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There are a few bugs in the cpu/mpc83xx/spd_sdram.c
the first bug is that the picos_to_clk routine introduces a huge
rounding error in 83xx.
the second bug is that the mode register write recovery field is
tWR-1, not tWR >> 1.
This commit is contained in:
Xie Xiaobo 2007-03-09 19:08:25 +08:00 committed by Kim Phillips
parent aea17f9927
commit 6fbf261f8d
1 changed files with 3 additions and 3 deletions
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6
cpu/mpc83xx/spd_sdram.c
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@ -58,8 +58,8 @@ picos_to_clk(int picos)
int clks; int clks;
ddr_bus_clk = gd->ddr_clk >> 1; ddr_bus_clk = gd->ddr_clk >> 1;
clks = picos / ((1000000000 / ddr_bus_clk) * 1000); clks = picos / (1000000000 / (ddr_bus_clk / 1000));
if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0) if (picos % (1000000000 / (ddr_bus_clk / 1000)) != 0)
clks++; clks++;
return clks; return clks;
@ -624,7 +624,7 @@ long int spd_sdram()
| (1 << (16 + 10)) /* DQS Differential disable */ | (1 << (16 + 10)) /* DQS Differential disable */
| (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
| (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
| ((twr_clk >> 1) << 9) /* Write Recovery Autopre */ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
| (caslat << 4) /* caslat */ | (caslat << 4) /* caslat */
| (burstlen << 0) /* Burst length */ | (burstlen << 0) /* Burst length */
); );