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https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-11 13:08:31 -04:00
Cleanup
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49a7581c6c
commit
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@ -36,7 +36,7 @@
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#include <common.h>
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#include <common.h>
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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# include <pci.h>
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#include <pci.h>
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#endif
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#endif
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void flash__init (void);
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void flash__init (void);
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@ -385,4 +385,3 @@ u32 get_device_type(void)
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mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
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mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
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return(mode >>= 8);
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return(mode >>= 8);
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}
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}
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@ -55,7 +55,6 @@
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# define CFG_LOWBOOT 1
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# define CFG_LOWBOOT 1
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#endif
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#endif
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/* ADS flavours */
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/* ADS flavours */
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#define CFG_8260ADS 1 /* MPC8260ADS */
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#define CFG_8260ADS 1 /* MPC8260ADS */
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#define CFG_8266ADS 2 /* MPC8266ADS */
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#define CFG_8266ADS 2 /* MPC8266ADS */
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@ -185,7 +184,6 @@
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#endif
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#ifndef CONFIG_SDRAM_PBI
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#ifndef CONFIG_SDRAM_PBI
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#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
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#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
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#endif
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#endif
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@ -334,7 +332,6 @@
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#ifdef CFG_LOWBOOT
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#ifdef CFG_LOWBOOT
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/* PQ2FADS flash HRCW = 0x0EB4B645 */
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/* PQ2FADS flash HRCW = 0x0EB4B645 */
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#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
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#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
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@ -386,13 +383,11 @@
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# define CFG_ENV_SIZE 0x200
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# define CFG_ENV_SIZE 0x200
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#endif /* CFG_RAMBOOT */
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#endif /* CFG_RAMBOOT */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#endif
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#define CFG_HID0_INIT 0
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#define CFG_HID0_INIT 0
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
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#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
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@ -461,8 +456,6 @@
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* these windows.
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* these windows.
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*/
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*/
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/*
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/*
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* Master window that allows the CPU to access PCI Memory (prefetch).
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* Master window that allows the CPU to access PCI Memory (prefetch).
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* This window will be setup with the second set of Outbound ATU registers
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* This window will be setup with the second set of Outbound ATU registers
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@ -314,4 +314,3 @@
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* - PLL BYPASS b00
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* - PLL BYPASS b00
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*/
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*/
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#endif /* __CONFIG_H */
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#endif /* __CONFIG_H */
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@ -40,7 +40,7 @@
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/* Clock config to target*/
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/* Clock config to target*/
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#define PRCM_CONFIG_II 1
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#define PRCM_CONFIG_II 1
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//#define PRCM_CONFIG_III 1
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/* #define PRCM_CONFIG_III 1 */
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#include <asm/arch/omap2420.h> /* get chip and board defs */
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#include <asm/arch/omap2420.h> /* get chip and board defs */
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@ -157,7 +157,6 @@
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#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
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#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
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#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
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#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_CLRALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_SETALE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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#define NAND_CTL_CLRCLE(nandptr)
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@ -165,7 +164,6 @@
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#define NAND_DISABLE_CE(nand)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTDELAY 3
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#ifdef NFS_BOOT_DEFAULTS
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#ifdef NFS_BOOT_DEFAULTS
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@ -261,9 +259,6 @@
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#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
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#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
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#endif
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#endif
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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* CFI FLASH driver setup
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*/
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*/
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