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Cleanup

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This commit is contained in:
Wolfgang Denk 2005-09-25 18:49:35 +02:00
parent 49a7581c6c
commit 716c1dcb41
10 changed files with 197 additions and 211 deletions
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26
board/integratorap/integratorap.c
View File

@ -36,7 +36,7 @@
#include <common.h> #include <common.h>
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
# include <pci.h> #include <pci.h>
#endif #endif
void flash__init (void); void flash__init (void);
@ -46,7 +46,7 @@ void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS) #if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress) void show_boot_progress(int progress)
{ {
printf("Boot reached stage %d\n", progress); printf("Boot reached stage %d\n", progress);
} }
#endif #endif
@ -483,7 +483,7 @@ int dram_init (void)
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT #ifdef CONFIG_CM_SPD_DETECT
{ {
@ -492,22 +492,22 @@ extern void dram_query(void);
unsigned long sdram_shift; unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */ dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */ /* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */ /* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size /* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
* *
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/ */
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
} }
#endif /* CM_SPD_DETECT */ #endif /* CM_SPD_DETECT */

1
board/omap2420h4/sys_info.c
View File

@ -385,4 +385,3 @@ u32 get_device_type(void)
mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
return(mode >>= 8); return(mode >>= 8);
} }

36
cpu/mpc8260/pci.c
View File

@ -254,24 +254,24 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_LBPC01; | SIUMCR_LBPC01;
#elif defined CONFIG_MPC8272 #elif defined CONFIG_MPC8272
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_BBD & ~SIUMCR_BBD &
~SIUMCR_ESE & ~SIUMCR_ESE &
~SIUMCR_PBSE & ~SIUMCR_PBSE &
~SIUMCR_CDIS & ~SIUMCR_CDIS &
~SIUMCR_DPPC11 & ~SIUMCR_DPPC11 &
~SIUMCR_L2CPC11 & ~SIUMCR_L2CPC11 &
~SIUMCR_LBPC11 & ~SIUMCR_LBPC11 &
~SIUMCR_APPC11 & ~SIUMCR_APPC11 &
~SIUMCR_CS10PC11 & ~SIUMCR_CS10PC11 &
~SIUMCR_BCTLC11 & ~SIUMCR_BCTLC11 &
~SIUMCR_MMR11) ~SIUMCR_MMR11)
| SIUMCR_DPPC11 | SIUMCR_DPPC11
| SIUMCR_L2CPC01 | SIUMCR_L2CPC01
| SIUMCR_LBPC00 | SIUMCR_LBPC00
| SIUMCR_APPC10 | SIUMCR_APPC10
| SIUMCR_CS10PC00 | SIUMCR_CS10PC00
| SIUMCR_BCTLC00 | SIUMCR_BCTLC00
| SIUMCR_MMR11; | SIUMCR_MMR11;
#else #else
/* /*

7
include/configs/MPC8260ADS.h
View File

@ -55,7 +55,6 @@
# define CFG_LOWBOOT 1 # define CFG_LOWBOOT 1
#endif #endif
/* ADS flavours */ /* ADS flavours */
#define CFG_8260ADS 1 /* MPC8260ADS */ #define CFG_8260ADS 1 /* MPC8260ADS */
#define CFG_8266ADS 2 /* MPC8266ADS */ #define CFG_8266ADS 2 /* MPC8266ADS */
@ -185,7 +184,6 @@
#define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCI_SCAN_SHOW
#endif #endif
#ifndef CONFIG_SDRAM_PBI #ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#endif #endif
@ -334,7 +332,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#ifdef CFG_LOWBOOT #ifdef CFG_LOWBOOT
/* PQ2FADS flash HRCW = 0x0EB4B645 */ /* PQ2FADS flash HRCW = 0x0EB4B645 */
#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
@ -386,13 +383,11 @@
# define CFG_ENV_SIZE 0x200 # define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */ #endif /* CFG_RAMBOOT */
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif #endif
#define CFG_HID0_INIT 0 #define CFG_HID0_INIT 0
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
@ -461,8 +456,6 @@
* these windows. * these windows.
*/ */
/* /*
* Master window that allows the CPU to access PCI Memory (prefetch). * Master window that allows the CPU to access PCI Memory (prefetch).
* This window will be setup with the second set of Outbound ATU registers * This window will be setup with the second set of Outbound ATU registers

243
include/configs/integratorap.h
View File

@ -38,15 +38,15 @@
#define CFG_MEMTEST_END 0x10000000 #define CFG_MEMTEST_END 0x10000000
#define CFG_HZ 1000 #define CFG_HZ 1000
#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ #define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
#define CFG_TIMERBASE 0x13000100 /* Timer1 */ #define CFG_TIMERBASE 0x13000100 /* Timer1 */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
#undef CONFIG_INIT_CRITICAL #undef CONFIG_INIT_CRITICAL
#define CONFIG_CM_INIT 1 #define CONFIG_CM_INIT 1
#define CONFIG_CM_REMAP 1 #define CONFIG_CM_REMAP 1
#undef CONFIG_CM_SPD_DETECT #undef CONFIG_CM_SPD_DETECT
/* /*
@ -60,36 +60,36 @@
*/ */
#define CFG_PL010_SERIAL #define CFG_PL010_SERIAL
#define CONFIG_CONS_INDEX 0 #define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400 #define CONFIG_BAUDRATE 38400
#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000 #define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000 #define CFG_SERIAL1 0x17000000
/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ /*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
/*#define CONFIG_NET_MULTI */ /*#define CONFIG_NET_MULTI */
/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ /*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) #define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
#define CONFIG_BOOTCOMMAND "" #define CONFIG_BOOTCOMMAND ""
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */ /* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ #define CFG_LOAD_ADDR 0x7fc0 /* default load address */
@ -108,11 +108,11 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Physical Memory Map * Physical Memory Map
*/ */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CFG_FLASH_BASE 0x24000000 #define CFG_FLASH_BASE 0x24000000
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH and environment organization * FLASH and environment organization
@ -123,8 +123,8 @@
/* timeout values are in ticks */ /* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_MAX_FLASH_SECT 128 #define CFG_MAX_FLASH_SECT 128
#define CFG_ENV_SIZE 32768 #define CFG_ENV_SIZE 32768
#define PHYS_FLASH_1 (CFG_FLASH_BASE) #define PHYS_FLASH_1 (CFG_FLASH_BASE)
@ -134,35 +134,35 @@
/*#define CONFIG_PCI /--* include pci support */ /*#define CONFIG_PCI /--* include pci support */
#undef CONFIG_PCI_PNP #undef CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define DEBUG #define DEBUG
#define CONFIG_EEPRO100 #define CONFIG_EEPRO100
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
/* PCI Base area */ /* PCI Base area */
#define INTEGRATOR_PCI_BASE 0x40000000 #define INTEGRATOR_PCI_BASE 0x40000000
#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
/* memory map as seen by the CPU on the local bus */ /* memory map as seen by the CPU on the local bus */
#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
#define CPU_PCI_IO_SIZE 0x10000 #define CPU_PCI_IO_SIZE 0x10000
#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
#define CPU_PCI_CNFG_SIZE 0x1000000 #define CPU_PCI_CNFG_SIZE 0x1000000
#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
/* unused (128-16)M from B1000000-B7FFFFFF */ /* unused (128-16)M from B1000000-B7FFFFFF */
#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
/* unused ((128-16)M - 64K) from XXX */ /* unused ((128-16)M - 64K) from XXX */
#define PCI_V3_BASE 0x62000000 #define PCI_V3_BASE 0x62000000
/* V3 PCI bridge controller */ /* V3 PCI bridge controller */
#define V3_BASE 0x62000000 /* V360EPC registers */ #define V3_BASE 0x62000000 /* V360EPC registers */
@ -171,97 +171,97 @@
#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) #define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
#define V3_PCI_VENDOR 0x00000000 #define V3_PCI_VENDOR 0x00000000
#define V3_PCI_DEVICE 0x00000002 #define V3_PCI_DEVICE 0x00000002
#define V3_PCI_CMD 0x00000004 #define V3_PCI_CMD 0x00000004
#define V3_PCI_STAT 0x00000006 #define V3_PCI_STAT 0x00000006
#define V3_PCI_CC_REV 0x00000008 #define V3_PCI_CC_REV 0x00000008
#define V3_PCI_HDR_CF 0x0000000C #define V3_PCI_HDR_CF 0x0000000C
#define V3_PCI_IO_BASE 0x00000010 #define V3_PCI_IO_BASE 0x00000010
#define V3_PCI_BASE0 0x00000014 #define V3_PCI_BASE0 0x00000014
#define V3_PCI_BASE1 0x00000018 #define V3_PCI_BASE1 0x00000018
#define V3_PCI_SUB_VENDOR 0x0000002C #define V3_PCI_SUB_VENDOR 0x0000002C
#define V3_PCI_SUB_ID 0x0000002E #define V3_PCI_SUB_ID 0x0000002E
#define V3_PCI_ROM 0x00000030 #define V3_PCI_ROM 0x00000030
#define V3_PCI_BPARAM 0x0000003C #define V3_PCI_BPARAM 0x0000003C
#define V3_PCI_MAP0 0x00000040 #define V3_PCI_MAP0 0x00000040
#define V3_PCI_MAP1 0x00000044 #define V3_PCI_MAP1 0x00000044
#define V3_PCI_INT_STAT 0x00000048 #define V3_PCI_INT_STAT 0x00000048
#define V3_PCI_INT_CFG 0x0000004C #define V3_PCI_INT_CFG 0x0000004C
#define V3_LB_BASE0 0x00000054 #define V3_LB_BASE0 0x00000054
#define V3_LB_BASE1 0x00000058 #define V3_LB_BASE1 0x00000058
#define V3_LB_MAP0 0x0000005E #define V3_LB_MAP0 0x0000005E
#define V3_LB_MAP1 0x00000062 #define V3_LB_MAP1 0x00000062
#define V3_LB_BASE2 0x00000064 #define V3_LB_BASE2 0x00000064
#define V3_LB_MAP2 0x00000066 #define V3_LB_MAP2 0x00000066
#define V3_LB_SIZE 0x00000068 #define V3_LB_SIZE 0x00000068
#define V3_LB_IO_BASE 0x0000006E #define V3_LB_IO_BASE 0x0000006E
#define V3_FIFO_CFG 0x00000070 #define V3_FIFO_CFG 0x00000070
#define V3_FIFO_PRIORITY 0x00000072 #define V3_FIFO_PRIORITY 0x00000072
#define V3_FIFO_STAT 0x00000074 #define V3_FIFO_STAT 0x00000074
#define V3_LB_ISTAT 0x00000076 #define V3_LB_ISTAT 0x00000076
#define V3_LB_IMASK 0x00000077 #define V3_LB_IMASK 0x00000077
#define V3_SYSTEM 0x00000078 #define V3_SYSTEM 0x00000078
#define V3_LB_CFG 0x0000007A #define V3_LB_CFG 0x0000007A
#define V3_PCI_CFG 0x0000007C #define V3_PCI_CFG 0x0000007C
#define V3_DMA_PCI_ADR0 0x00000080 #define V3_DMA_PCI_ADR0 0x00000080
#define V3_DMA_PCI_ADR1 0x00000090 #define V3_DMA_PCI_ADR1 0x00000090
#define V3_DMA_LOCAL_ADR0 0x00000084 #define V3_DMA_LOCAL_ADR0 0x00000084
#define V3_DMA_LOCAL_ADR1 0x00000094 #define V3_DMA_LOCAL_ADR1 0x00000094
#define V3_DMA_LENGTH0 0x00000088 #define V3_DMA_LENGTH0 0x00000088
#define V3_DMA_LENGTH1 0x00000098 #define V3_DMA_LENGTH1 0x00000098
#define V3_DMA_CSR0 0x0000008B #define V3_DMA_CSR0 0x0000008B
#define V3_DMA_CSR1 0x0000009B #define V3_DMA_CSR1 0x0000009B
#define V3_DMA_CTLB_ADR0 0x0000008C #define V3_DMA_CTLB_ADR0 0x0000008C
#define V3_DMA_CTLB_ADR1 0x0000009C #define V3_DMA_CTLB_ADR1 0x0000009C
#define V3_DMA_DELAY 0x000000E0 #define V3_DMA_DELAY 0x000000E0
#define V3_MAIL_DATA 0x000000C0 #define V3_MAIL_DATA 0x000000C0
#define V3_PCI_MAIL_IEWR 0x000000D0 #define V3_PCI_MAIL_IEWR 0x000000D0
#define V3_PCI_MAIL_IERD 0x000000D2 #define V3_PCI_MAIL_IERD 0x000000D2
#define V3_LB_MAIL_IEWR 0x000000D4 #define V3_LB_MAIL_IEWR 0x000000D4
#define V3_LB_MAIL_IERD 0x000000D6 #define V3_LB_MAIL_IERD 0x000000D6
#define V3_MAIL_WR_STAT 0x000000D8 #define V3_MAIL_WR_STAT 0x000000D8
#define V3_MAIL_RD_STAT 0x000000DA #define V3_MAIL_RD_STAT 0x000000DA
#define V3_QBA_MAP 0x000000DC #define V3_QBA_MAP 0x000000DC
/* SYSTEM register bits */ /* SYSTEM register bits */
#define V3_SYSTEM_M_RST_OUT (1 << 15) #define V3_SYSTEM_M_RST_OUT (1 << 15)
#define V3_SYSTEM_M_LOCK (1 << 14) #define V3_SYSTEM_M_LOCK (1 << 14)
/* PCI_CFG bits */ /* PCI_CFG bits */
#define V3_PCI_CFG_M_RETRY_EN (1 << 10) #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
/* PCI MAP register bits (PCI -> Local bus) */ /* PCI MAP register bits (PCI -> Local bus) */
#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
#define V3_PCI_MAP_M_REG_EN (1 << 1) #define V3_PCI_MAP_M_REG_EN (1 << 1)
#define V3_PCI_MAP_M_ENABLE (1 << 0) #define V3_PCI_MAP_M_ENABLE (1 << 0)
/* 9 => 512M window size */ /* 9 => 512M window size */
#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
/* A => 1024M window size */ /* A => 1024M window size */
#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
/* LB_BASE register bits (Local bus -> PCI) */ /* LB_BASE register bits (Local bus -> PCI) */
#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000
#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0
#define V3_LB_BASE_M_PREFETCH (1 << 3) #define V3_LB_BASE_M_PREFETCH (1 << 3)
#define V3_LB_BASE_M_ENABLE (1 << 0) #define V3_LB_BASE_M_ENABLE (1 << 0)
/* PCI COMMAND REGISTER bits */ /* PCI COMMAND REGISTER bits */
#define V3_COMMAND_M_FBB_EN (1 << 9) #define V3_COMMAND_M_FBB_EN (1 << 9)
#define V3_COMMAND_M_SERR_EN (1 << 8) #define V3_COMMAND_M_SERR_EN (1 << 8)
#define V3_COMMAND_M_PAR_EN (1 << 6) #define V3_COMMAND_M_PAR_EN (1 << 6)
#define V3_COMMAND_M_MASTER_EN (1 << 2) #define V3_COMMAND_M_MASTER_EN (1 << 2)
#define V3_COMMAND_M_MEM_EN (1 << 1) #define V3_COMMAND_M_MEM_EN (1 << 1)
#define V3_COMMAND_M_IO_EN (1 << 0) #define V3_COMMAND_M_IO_EN (1 << 0)
#define INTEGRATOR_SC_BASE 0x11000000 #define INTEGRATOR_SC_BASE 0x11000000
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
@ -280,38 +280,37 @@
/* CM registers common to all integrator/CP CMs */ /* CM registers common to all integrator/CP CMs */
#define OS_CTRL 0x0000000C #define OS_CTRL 0x0000000C
#define CMMASK_REMAP 0x00000005 /* Set remap & led */ #define CMMASK_REMAP 0x00000005 /* Set remap & led */
#define CMMASK_RESET 0x00000008 #define CMMASK_RESET 0x00000008
#define OS_LOCK 0x00000014 #define OS_LOCK 0x00000014
#define CMVAL_LOCK 0x0000A000 /* Locking value */ #define CMVAL_LOCK 0x0000A000 /* Locking value */
#define CMMASK_LOCK 0x0000005F /* Locking value */ #define CMMASK_LOCK 0x0000005F /* Locking value */
#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */ #define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
#define OS_SDRAM 0x00000020 #define OS_SDRAM 0x00000020
#define OS_INIT 0x00000024 #define OS_INIT 0x00000024
#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ #define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
#ifdef CONFIG_CM_SPD_DETECT #ifdef CONFIG_CM_SPD_DETECT
#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ #define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
#endif #endif
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual #define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
* - PLL test clock bypassed * - PLL test clock bypassed
* - bus clock ratio 2 * - bus clock ratio 2
* - little endian * - little endian
* - vectors at zero * - vectors at zero
*/ */
#endif /* CM1022xx */ #endif /* CM1022xx */
#define CMMASK_LE 0x00000008 /* little endian */ #define CMMASK_LE 0x00000008 /* little endian */
#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6 #define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
* - divisor/ratio b00000001 * - divisor/ratio b00000001
* bx * bx
* - HCLKDIV b000 * - HCLKDIV b000
* bxx * bxx
* - PLL BYPASS b00 * - PLL BYPASS b00
*/ */
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

7
include/configs/omap2420h4.h
View File

@ -40,7 +40,7 @@
/* Clock config to target*/ /* Clock config to target*/
#define PRCM_CONFIG_II 1 #define PRCM_CONFIG_II 1
//#define PRCM_CONFIG_III 1 /* #define PRCM_CONFIG_III 1 */
#include <asm/arch/omap2420.h> /* get chip and board defs */ #include <asm/arch/omap2420.h> /* get chip and board defs */
@ -157,7 +157,6 @@
#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) #define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) #define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
#define NAND_CTL_CLRALE(nandptr) #define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr) #define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr) #define NAND_CTL_CLRCLE(nandptr)
@ -165,7 +164,6 @@
#define NAND_DISABLE_CE(nand) #define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand) #define NAND_ENABLE_CE(nand)
#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS #ifdef NFS_BOOT_DEFAULTS
@ -261,9 +259,6 @@
#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ #define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
#endif #endif
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* CFI FLASH driver setup * CFI FLASH driver setup
*/ */