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ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)

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Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-06-01 13:45:00 +02:00
parent 19bf91f962
commit 7187db7349
1 changed files with 6 additions and 1 deletions
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7
cpu/ppc4xx/44x_spd_ddr2.c
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@ -465,7 +465,11 @@ long int initdram(int board_type)
* Set the SDRAM Clock Timing Register * Set the SDRAM Clock Timing Register
*-----------------------------------------------------------------*/ *-----------------------------------------------------------------*/
mfsdram(SDRAM_CLKTR, val); mfsdram(SDRAM_CLKTR, val);
#ifdef CFG_44x_DDR2_CKTR_180
mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
#else
mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG); mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
#endif
/*------------------------------------------------------------------ /*------------------------------------------------------------------
* Program the BxCF registers. * Program the BxCF registers.
@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated,
modt3 = 0x00000000; modt3 = 0x00000000;
} }
if (total_rank == 4) { if (total_rank == 4) {
codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3); codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
CALC_ODT_R(2) | CALC_ODT_R(3);
modt0 = CALC_ODT_RW(2); modt0 = CALC_ODT_RW(2);
modt1 = 0x00000000; modt1 = 0x00000000;
modt2 = CALC_ODT_RW(0); modt2 = CALC_ODT_RW(0);