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x86: turn off cache: set control register properly

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Bits should be ORed when they are supposed to be added together

Signed-off-by: Ondrej Kupka <ondra.cap@gmail.com>
This commit is contained in:
Ondrej Kupka 2011-09-30 21:05:11 +11:00 committed by Graeme Russ
parent ce5207e191
commit 7b3d5380ee
1 changed files with 1 additions and 1 deletions
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2
arch/x86/cpu/start16.S
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@ -50,7 +50,7 @@ board_init16_ret:
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
orl $(X86_CR0_NW & X86_CR0_CD), %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd