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OMAP5: board: Add pinmux data for omap5_evm board.

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Adding the full pinmux data for OMAP5430 sevm board.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
This commit is contained in:
SRICHARAN R 2012-03-12 02:25:35 +00:00 committed by Albert ARIBAUD
parent 5f14d9197e
commit 84b16af29f
2 changed files with 509 additions and 482 deletions
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502
arch/arm/include/asm/arch-omap5/mux_omap5.h
View File

@ -87,258 +87,256 @@ struct pad_conf_entry {
#define CORE_REVISION 0x0000 #define CORE_REVISION 0x0000
#define CORE_HWINFO 0x0004 #define CORE_HWINFO 0x0004
#define CORE_SYSCONFIG 0x0010 #define CORE_SYSCONFIG 0x0010
#define GPMC_AD0 0x0040 #define EMMC_CLK 0x0040
#define GPMC_AD1 0x0042 #define EMMC_CMD 0x0042
#define GPMC_AD2 0x0044 #define EMMC_DATA0 0x0044
#define GPMC_AD3 0x0046 #define EMMC_DATA1 0x0046
#define GPMC_AD4 0x0048 #define EMMC_DATA2 0x0048
#define GPMC_AD5 0x004A #define EMMC_DATA3 0x004a
#define GPMC_AD6 0x004C #define EMMC_DATA4 0x004c
#define GPMC_AD7 0x004E #define EMMC_DATA5 0x004e
#define GPMC_AD8 0x0050 #define EMMC_DATA6 0x0050
#define GPMC_AD9 0x0052 #define EMMC_DATA7 0x0052
#define GPMC_AD10 0x0054 #define C2C_CLKOUT0 0x0054
#define GPMC_AD11 0x0056 #define C2C_CLKOUT1 0x0056
#define GPMC_AD12 0x0058 #define C2C_CLKIN0 0x0058
#define GPMC_AD13 0x005A #define C2C_CLKIN1 0x005a
#define GPMC_AD14 0x005C #define C2C_DATAIN0 0x005c
#define GPMC_AD15 0x005E #define C2C_DATAIN1 0x005e
#define GPMC_A16 0x0060 #define C2C_DATAIN2 0x0060
#define GPMC_A17 0x0062 #define C2C_DATAIN3 0x0062
#define GPMC_A18 0x0064 #define C2C_DATAIN4 0x0064
#define GPMC_A19 0x0066 #define C2C_DATAIN5 0x0066
#define GPMC_A20 0x0068 #define C2C_DATAIN6 0x0068
#define GPMC_A21 0x006A #define C2C_DATAIN7 0x006a
#define GPMC_A22 0x006C #define C2C_DATAOUT0 0x006c
#define GPMC_A23 0x006E #define C2C_DATAOUT1 0x006e
#define GPMC_A24 0x0070 #define C2C_DATAOUT2 0x0070
#define GPMC_A25 0x0072 #define C2C_DATAOUT3 0x0072
#define GPMC_NCS0 0x0074 #define C2C_DATAOUT4 0x0074
#define GPMC_NCS1 0x0076 #define C2C_DATAOUT5 0x0076
#define GPMC_NCS2 0x0078 #define C2C_DATAOUT6 0x0078
#define GPMC_NCS3 0x007A #define C2C_DATAOUT7 0x007a
#define GPMC_NWP 0x007C #define C2C_DATA8 0x007c
#define GPMC_CLK 0x007E #define C2C_DATA9 0x007e
#define GPMC_NADV_ALE 0x0080 #define C2C_DATA10 0x0080
#define GPMC_NOE 0x0082 #define C2C_DATA11 0x0082
#define GPMC_NWE 0x0084 #define C2C_DATA12 0x0084
#define GPMC_NBE0_CLE 0x0086 #define C2C_DATA13 0x0086
#define GPMC_NBE1 0x0088 #define C2C_DATA14 0x0088
#define GPMC_WAIT0 0x008A #define C2C_DATA15 0x008a
#define GPMC_WAIT1 0x008C #define LLIA_WAKEREQOUT 0x008c
#define C2C_DATA11 0x008E #define LLIB_WAKEREQOUT 0x008e
#define C2C_DATA12 0x0090 #define HSI1_ACREADY 0x0090
#define C2C_DATA13 0x0092 #define HSI1_CAREADY 0x0092
#define C2C_DATA14 0x0094 #define HSI1_ACWAKE 0x0094
#define C2C_DATA15 0x0096 #define HSI1_CAWAKE 0x0096
#define HDMI_HPD 0x0098 #define HSI1_ACFLAG 0x0098
#define HDMI_CEC 0x009A #define HSI1_ACDATA 0x009a
#define HDMI_DDC_SCL 0x009C #define HSI1_CAFLAG 0x009c
#define HDMI_DDC_SDA 0x009E #define HSI1_CADATA 0x009e
#define CSI21_DX0 0x00A0 #define UART1_TX 0x00a0
#define CSI21_DY0 0x00A2 #define UART1_CTS 0x00a2
#define CSI21_DX1 0x00A4 #define UART1_RX 0x00a4
#define CSI21_DY1 0x00A6 #define UART1_RTS 0x00a6
#define CSI21_DX2 0x00A8 #define HSI2_CAREADY 0x00a8
#define CSI21_DY2 0x00AA #define HSI2_ACREADY 0x00aa
#define CSI21_DX3 0x00AC #define HSI2_CAWAKE 0x00ac
#define CSI21_DY3 0x00AE #define HSI2_ACWAKE 0x00ae
#define CSI21_DX4 0x00B0 #define HSI2_CAFLAG 0x00b0
#define CSI21_DY4 0x00B2 #define HSI2_CADATA 0x00b2
#define CSI22_DX0 0x00B4 #define HSI2_ACFLAG 0x00b4
#define CSI22_DY0 0x00B6 #define HSI2_ACDATA 0x00b6
#define CSI22_DX1 0x00B8 #define UART2_RTS 0x00b8
#define CSI22_DY1 0x00BA #define UART2_CTS 0x00ba
#define CAM_SHUTTER 0x00BC #define UART2_RX 0x00bc
#define CAM_STROBE 0x00BE #define UART2_TX 0x00be
#define CAM_GLOBALRESET 0x00C0 #define USBB1_HSIC_STROBE 0x00c0
#define USBB1_ULPITLL_CLK 0x00C2 #define USBB1_HSIC_DATA 0x00c2
#define USBB1_ULPITLL_STP 0x00C4 #define USBB2_HSIC_STROBE 0x00c4
#define USBB1_ULPITLL_DIR 0x00C6 #define USBB2_HSIC_DATA 0x00c6
#define USBB1_ULPITLL_NXT 0x00C8 #define TIMER10_PWM_EVT 0x00c8
#define USBB1_ULPITLL_DAT0 0x00CA #define DSIPORTA_TE0 0x00ca
#define USBB1_ULPITLL_DAT1 0x00CC #define DSIPORTA_LANE0X 0x00cc
#define USBB1_ULPITLL_DAT2 0x00CE #define DSIPORTA_LANE0Y 0x00ce
#define USBB1_ULPITLL_DAT3 0x00D0 #define DSIPORTA_LANE1X 0x00d0
#define USBB1_ULPITLL_DAT4 0x00D2 #define DSIPORTA_LANE1Y 0x00d2
#define USBB1_ULPITLL_DAT5 0x00D4 #define DSIPORTA_LANE2X 0x00d4
#define USBB1_ULPITLL_DAT6 0x00D6 #define DSIPORTA_LANE2Y 0x00d6
#define USBB1_ULPITLL_DAT7 0x00D8 #define DSIPORTA_LANE3X 0x00d8
#define USBB1_HSIC_DATA 0x00DA #define DSIPORTA_LANE3Y 0x00da
#define USBB1_HSIC_STROBE 0x00DC #define DSIPORTA_LANE4X 0x00dc
#define USBC1_ICUSB_DP 0x00DE #define DSIPORTA_LANE4Y 0x00de
#define USBC1_ICUSB_DM 0x00E0 #define DSIPORTC_LANE0X 0x00e0
#define SDMMC1_CLK 0x00E2 #define DSIPORTC_LANE0Y 0x00e2
#define SDMMC1_CMD 0x00E4 #define DSIPORTC_LANE1X 0x00e4
#define SDMMC1_DAT0 0x00E6 #define DSIPORTC_LANE1Y 0x00e6
#define SDMMC1_DAT1 0x00E8 #define DSIPORTC_LANE2X 0x00e8
#define SDMMC1_DAT2 0x00EA #define DSIPORTC_LANE2Y 0x00ea
#define SDMMC1_DAT3 0x00EC #define DSIPORTC_LANE3X 0x00ec
#define SDMMC1_DAT4 0x00EE #define DSIPORTC_LANE3Y 0x00ee
#define SDMMC1_DAT5 0x00F0 #define DSIPORTC_LANE4X 0x00f0
#define SDMMC1_DAT6 0x00F2 #define DSIPORTC_LANE4Y 0x00f2
#define SDMMC1_DAT7 0x00F4 #define DSIPORTC_TE0 0x00f4
#define ABE_MCBSP2_CLKX 0x00F6 #define TIMER9_PWM_EVT 0x00f6
#define ABE_MCBSP2_DR 0x00F8 #define I2C4_SCL 0x00f8
#define ABE_MCBSP2_DX 0x00FA #define I2C4_SDA 0x00fa
#define ABE_MCBSP2_FSX 0x00FC #define MCSPI2_CLK 0x00fc
#define ABE_MCBSP1_CLKX 0x00FE #define MCSPI2_SIMO 0x00fe
#define ABE_MCBSP1_DR 0x0100 #define MCSPI2_SOMI 0x0100
#define ABE_MCBSP1_DX 0x0102 #define MCSPI2_CS0 0x0102
#define ABE_MCBSP1_FSX 0x0104 #define RFBI_DATA15 0x0104
#define ABE_PDM_UL_DATA 0x0106 #define RFBI_DATA14 0x0106
#define ABE_PDM_DL_DATA 0x0108 #define RFBI_DATA13 0x0108
#define ABE_PDM_FRAME 0x010A #define RFBI_DATA12 0x010a
#define ABE_PDM_LB_CLK 0x010C #define RFBI_DATA11 0x010c
#define ABE_CLKS 0x010E #define RFBI_DATA10 0x010e
#define ABE_DMIC_CLK1 0x0110 #define RFBI_DATA9 0x0110
#define ABE_DMIC_DIN1 0x0112 #define RFBI_DATA8 0x0112
#define ABE_DMIC_DIN2 0x0114 #define RFBI_DATA7 0x0114
#define ABE_DMIC_DIN3 0x0116 #define RFBI_DATA6 0x0116
#define UART2_CTS 0x0118 #define RFBI_DATA5 0x0118
#define UART2_RTS 0x011A #define RFBI_DATA4 0x011a
#define UART2_RX 0x011C #define RFBI_DATA3 0x011c
#define UART2_TX 0x011E #define RFBI_DATA2 0x011e
#define HDQ_SIO 0x0120 #define RFBI_DATA1 0x0120
#define I2C1_SCL 0x0122 #define RFBI_DATA0 0x0122
#define I2C1_SDA 0x0124 #define RFBI_WE 0x0124
#define I2C2_SCL 0x0126 #define RFBI_CS0 0x0126
#define I2C2_SDA 0x0128 #define RFBI_A0 0x0128
#define I2C3_SCL 0x012A #define RFBI_RE 0x012a
#define I2C3_SDA 0x012C #define RFBI_HSYNC0 0x012c
#define I2C4_SCL 0x012E #define RFBI_TE_VSYNC0 0x012e
#define I2C4_SDA 0x0130 #define GPIO6_182 0x0130
#define MCSPI1_CLK 0x0132 #define GPIO6_183 0x0132
#define MCSPI1_SOMI 0x0134 #define GPIO6_184 0x0134
#define MCSPI1_SIMO 0x0136 #define GPIO6_185 0x0136
#define MCSPI1_CS0 0x0138 #define GPIO6_186 0x0138
#define MCSPI1_CS1 0x013A #define GPIO6_187 0x013a
#define MCSPI1_CS2 0x013C #define HDMI_CEC 0x013c
#define MCSPI1_CS3 0x013E #define HDMI_HPD 0x013e
#define UART3_CTS_RCTX 0x0140 #define HDMI_DDC_SCL 0x0140
#define UART3_RTS_SD 0x0142 #define HDMI_DDC_SDA 0x0142
#define UART3_RX_IRRX 0x0144 #define CSIPORTC_LANE0X 0x0144
#define UART3_TX_IRTX 0x0146 #define CSIPORTC_LANE0Y 0x0146
#define SDMMC5_CLK 0x0148 #define CSIPORTC_LANE1X 0x0148
#define SDMMC5_CMD 0x014A #define CSIPORTC_LANE1Y 0x014a
#define SDMMC5_DAT0 0x014C #define CSIPORTB_LANE0X 0x014c
#define SDMMC5_DAT1 0x014E #define CSIPORTB_LANE0Y 0x014e
#define SDMMC5_DAT2 0x0150 #define CSIPORTB_LANE1X 0x0150
#define SDMMC5_DAT3 0x0152 #define CSIPORTB_LANE1Y 0x0152
#define MCSPI4_CLK 0x0154 #define CSIPORTB_LANE2X 0x0154
#define MCSPI4_SIMO 0x0156 #define CSIPORTB_LANE2Y 0x0156
#define MCSPI4_SOMI 0x0158 #define CSIPORTA_LANE0X 0x0158
#define MCSPI4_CS0 0x015A #define CSIPORTA_LANE0Y 0x015a
#define UART4_RX 0x015C #define CSIPORTA_LANE1X 0x015c
#define UART4_TX 0x015E #define CSIPORTA_LANE1Y 0x015e
#define USBB2_ULPITLL_CLK 0x0160 #define CSIPORTA_LANE2X 0x0160
#define USBB2_ULPITLL_STP 0x0162 #define CSIPORTA_LANE2Y 0x0162
#define USBB2_ULPITLL_DIR 0x0164 #define CSIPORTA_LANE3X 0x0164
#define USBB2_ULPITLL_NXT 0x0166 #define CSIPORTA_LANE3Y 0x0166
#define USBB2_ULPITLL_DAT0 0x0168 #define CSIPORTA_LANE4X 0x0168
#define USBB2_ULPITLL_DAT1 0x016A #define CSIPORTA_LANE4Y 0x016a
#define USBB2_ULPITLL_DAT2 0x016C #define CAM_SHUTTER 0x016c
#define USBB2_ULPITLL_DAT3 0x016E #define CAM_STROBE 0x016e
#define USBB2_ULPITLL_DAT4 0x0170 #define CAM_GLOBALRESET 0x0170
#define USBB2_ULPITLL_DAT5 0x0172 #define TIMER11_PWM_EVT 0x0172
#define USBB2_ULPITLL_DAT6 0x0174 #define TIMER5_PWM_EVT 0x0174
#define USBB2_ULPITLL_DAT7 0x0176 #define TIMER6_PWM_EVT 0x0176
#define USBB2_HSIC_DATA 0x0178 #define TIMER8_PWM_EVT 0x0178
#define USBB2_HSIC_STROBE 0x017A #define I2C3_SCL 0x017a
#define UNIPRO_TX0 0x017C #define I2C3_SDA 0x017c
#define UNIPRO_TY0 0x017E #define GPIO8_233 0x017e
#define UNIPRO_TX1 0x0180 #define GPIO8_234 0x0180
#define UNIPRO_TY1 0x0182 #define ABE_CLKS 0x0182
#define UNIPRO_TX2 0x0184 #define ABEDMIC_DIN1 0x0184
#define UNIPRO_TY2 0x0186 #define ABEDMIC_DIN2 0x0186
#define UNIPRO_RX0 0x0188 #define ABEDMIC_DIN3 0x0188
#define UNIPRO_RY0 0x018A #define ABEDMIC_CLK1 0x018a
#define UNIPRO_RX1 0x018C #define ABEDMIC_CLK2 0x018c
#define UNIPRO_RY1 0x018E #define ABEDMIC_CLK3 0x018e
#define UNIPRO_RX2 0x0190 #define ABESLIMBUS1_CLOCK 0x0190
#define UNIPRO_RY2 0x0192 #define ABESLIMBUS1_DATA 0x0192
#define USBA0_OTG_CE 0x0194 #define ABEMCBSP2_DR 0x0194
#define USBA0_OTG_DP 0x0196 #define ABEMCBSP2_DX 0x0196
#define USBA0_OTG_DM 0x0198 #define ABEMCBSP2_FSX 0x0198
#define FREF_CLK1_OUT 0x019A #define ABEMCBSP2_CLKX 0x019a
#define FREF_CLK2_OUT 0x019C #define ABEMCPDM_UL_DATA 0x019c
#define SYS_NIRQ1 0x019E #define ABEMCPDM_DL_DATA 0x019e
#define SYS_NIRQ2 0x01A0 #define ABEMCPDM_FRAME 0x01a0
#define SYS_BOOT0 0x01A2 #define ABEMCPDM_LB_CLK 0x01a2
#define SYS_BOOT1 0x01A4 #define WLSDIO_CLK 0x01a4
#define SYS_BOOT2 0x01A6 #define WLSDIO_CMD 0x01a6
#define SYS_BOOT3 0x01A8 #define WLSDIO_DATA0 0x01a8
#define SYS_BOOT4 0x01AA #define WLSDIO_DATA1 0x01aa
#define SYS_BOOT5 0x01AC #define WLSDIO_DATA2 0x01ac
#define DPM_EMU0 0x01AE #define WLSDIO_DATA3 0x01ae
#define DPM_EMU1 0x01B0 #define UART5_RX 0x01b0
#define DPM_EMU2 0x01B2 #define UART5_TX 0x01b2
#define DPM_EMU3 0x01B4 #define UART5_CTS 0x01b4
#define DPM_EMU4 0x01B6 #define UART5_RTS 0x01b6
#define DPM_EMU5 0x01B8 #define I2C2_SCL 0x01b8
#define DPM_EMU6 0x01BA #define I2C2_SDA 0x01ba
#define DPM_EMU7 0x01BC #define MCSPI1_CLK 0x01bc
#define DPM_EMU8 0x01BE #define MCSPI1_SOMI 0x01be
#define DPM_EMU9 0x01C0 #define MCSPI1_SIMO 0x01c0
#define DPM_EMU10 0x01C2 #define MCSPI1_CS0 0x01c2
#define DPM_EMU11 0x01C4 #define MCSPI1_CS1 0x01c4
#define DPM_EMU12 0x01C6 #define I2C5_SCL 0x01c6
#define DPM_EMU13 0x01C8 #define I2C5_SDA 0x01c8
#define DPM_EMU14 0x01CA #define PERSLIMBUS2_CLOCK 0x01ca
#define DPM_EMU15 0x01CC #define PERSLIMBUS2_DATA 0x01cc
#define DPM_EMU16 0x01CE #define UART6_TX 0x01ce
#define DPM_EMU17 0x01D0 #define UART6_RX 0x01d0
#define DPM_EMU18 0x01D2 #define UART6_CTS 0x01d2
#define DPM_EMU19 0x01D4 #define UART6_RTS 0x01d4
#define WAKEUPEVENT_0 0x01D8 #define UART3_CTS_RCTX 0x01d6
#define WAKEUPEVENT_1 0x01DC #define UART3_RTS_IRSD 0x01d8
#define WAKEUPEVENT_2 0x01E0 #define UART3_TX_IRTX 0x01da
#define WAKEUPEVENT_3 0x01E4 #define UART3_RX_IRRX 0x01dc
#define WAKEUPEVENT_4 0x01E8 #define USBB3_HSIC_STROBE 0x01de
#define WAKEUPEVENT_5 0x01EC #define USBB3_HSIC_DATA 0x01e0
#define WAKEUPEVENT_6 0x01F0 #define SDCARD_CLK 0x01e2
#define SDCARD_CMD 0x01e4
#define SDCARD_DATA2 0x01e6
#define SDCARD_DATA3 0x01e8
#define SDCARD_DATA0 0x01ea
#define SDCARD_DATA1 0x01ec
#define USBD0_HS_DP 0x01ee
#define USBD0_HS_DM 0x01f0
#define I2C1_PMIC_SCL 0x01f2
#define I2C1_PMIC_SDA 0x01f4
#define USBD0_SS_RX 0x01f6
#define WKUP_REVISION 0x0000 #define LLIA_WAKEREQIN 0x0040
#define WKUP_HWINFO 0x0004 #define LLIB_WAKEREQIN 0x0042
#define WKUP_SYSCONFIG 0x0010 #define DRM_EMU0 0x0044
#define PAD0_SIM_IO 0x0040 #define DRM_EMU1 0x0046
#define PAD1_SIM_CLK 0x0042 #define JTAG_NTRST 0x0048
#define PAD0_SIM_RESET 0x0044 #define JTAG_TCK 0x004a
#define PAD1_SIM_CD 0x0046 #define JTAG_RTCK 0x004c
#define PAD0_SIM_PWRCTRL 0x0048 #define JTAG_TMSC 0x004e
#define PAD1_SR_SCL 0x004A #define JTAG_TDI 0x0050
#define PAD0_SR_SDA 0x004C #define JTAG_TDO 0x0052
#define PAD1_FREF_XTAL_IN 0x004E #define SYS_32K 0x0054
#define PAD0_FREF_SLICER_IN 0x0050 #define FREF_CLK_IOREQ 0x0056
#define PAD1_FREF_CLK_IOREQ 0x0052 #define FREF_CLK0_OUT 0x0058
#define PAD0_FREF_CLK0_OUT 0x0054 #define FREF_CLK1_OUT 0x005a
#define PAD1_FREF_CLK3_REQ 0x0056 #define FREF_CLK2_OUT 0x005c
#define PAD0_FREF_CLK3_OUT 0x0058 #define FREF_CLK2_REQ 0x005e
#define PAD1_FREF_CLK4_REQ 0x005A #define FREF_CLK1_REQ 0x0060
#define PAD0_FREF_CLK4_OUT 0x005C #define SYS_NRESPWRON 0x0062
#define PAD1_SYS_32K 0x005E #define SYS_NRESWARM 0x0064
#define PAD0_SYS_NRESPWRON 0x0060 #define SYS_PWR_REQ 0x0066
#define PAD1_SYS_NRESWARM 0x0062 #define SYS_NIRQ1 0x0068
#define PAD0_SYS_PWR_REQ 0x0064 #define SYS_NIRQ2 0x006a
#define PAD1_SYS_PWRON_RESET 0x0066 #define SR_PMIC_SCL 0x006c
#define PAD0_SYS_BOOT6 0x0068 #define SR_PMIC_SDA 0x006e
#define PAD1_SYS_BOOT7 0x006A #define SYS_BOOT0 0x0070
#define PAD0_JTAG_NTRST 0x006C #define SYS_BOOT1 0x0072
#define PAD1_JTAG_TCK 0x006D #define SYS_BOOT2 0x0074
#define PAD0_JTAG_RTCK 0x0070 #define SYS_BOOT3 0x0076
#define PAD1_JTAG_TMS_TMSC 0x0072 #define SYS_BOOT4 0x0078
#define PAD0_JTAG_TDI 0x0074 #define SYS_BOOT5 0x007a
#define PAD1_JTAG_TDO 0x0076
#define PADCONF_WAKEUPEVENT_0 0x007C
#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
#define PADCONF_MODE 0x05A8
#define CONTROL_XTAL_OSCILLATOR 0x05AC
#define CONTROL_CONTROL_I2C_2 0x0604
#define CONTROL_CONTROL_JTAG 0x0608
#define CONTROL_CONTROL_SYS 0x060C
#define CONTROL_SPARE_RW 0x0614
#define CONTROL_SPARE_R 0x0618
#define CONTROL_SPARE_R_C0 0x061C
#endif /* _MUX_OMAP5_H_ */ #endif /* _MUX_OMAP5_H_ */

489
board/ti/omap5_evm/mux_data.h
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@ -2,8 +2,7 @@
* (C) Copyright 2010 * (C) Copyright 2010
* Texas Instruments Incorporated, <www.ti.com> * Texas Instruments Incorporated, <www.ti.com>
* *
* Balaji Krishnamoorthy <balajitk@ti.com> * Sricharan R <r.sricharan@ti.com>
* Aneesh V <aneesh@ti.com>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
@ -30,246 +29,276 @@
const struct pad_conf_entry core_padconf_array_essential[] = { const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)} /* uart3_tx */
}; };
const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ {SYS_32K, (IEN | M0)}, /* SYS_32K */
}; };
const struct pad_conf_entry core_padconf_array_non_essential[] = { const struct pad_conf_entry core_padconf_array_non_essential[] = {
{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
{GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */
{GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */
{GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */
{GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */
{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */
{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */
{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */
{GPMC_A16, (M3)}, /* gpio_40 */ {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */
{GPMC_A17, (PTD | M3)}, /* gpio_41 */ {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */
{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */
{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */
{GPMC_A20, (IEN | M3)}, /* gpio_44 */ {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */
{GPMC_A21, (M3)}, /* gpio_45 */ {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */
{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */
{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */
{GPMC_A24, (PTD | M3)}, /* gpio_48 */ {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */
{GPMC_A25, (PTD | M3)}, /* gpio_49 */ {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */
{GPMC_NCS0, (M3)}, /* gpio_50 */ {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */
{GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */
{GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */
{GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */
{GPMC_NWP, (M3)}, /* gpio_54 */ {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */
{GPMC_CLK, (PTD | M3)}, /* gpio_55 */ {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */
{GPMC_NADV_ALE, (M3)}, /* gpio_56 */ {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */
{GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */
{GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */
{GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */
{GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */
{C2C_DATA11, (PTD | M3)}, /* gpio_100 */ {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */
{C2C_DATA12, (M1)}, /* dsi1_te0 */ {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */
{C2C_DATA13, (PTD | M3)}, /* gpio_102 */ {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */
{C2C_DATA14, (M1)}, /* dsi2_te0 */ {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */
{C2C_DATA15, (PTD | M3)}, /* gpio_104 */ {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */
{HDMI_HPD, (M0)}, /* hdmi_hpd */ {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */
{HDMI_CEC, (M0)}, /* hdmi_cec */ {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */
{HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */
{HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */
{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ {HSI1_CADATA, (M6)}, /* GPIO3_71 */
{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ {UART1_TX, (M0)}, /* UART1_TX */
{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */
{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */
{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ {UART1_RTS, (M0)}, /* UART1_RTS */
{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */
{CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */
{CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */
{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */
{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */
{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */
{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */
{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */
{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */
{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */
{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */
{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */
{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
{USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
{USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */
{USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */
{USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */
{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */
{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */
{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */
{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */
{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */
{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */
{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */
{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ {RFBI_RE, (M4)}, /* KBD_COL4 */
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ {RFBI_DATA8, (M4)}, /* KBD_COL3 */
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */
{UART2_RTS, (M0)}, /* uart2_rts */ {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */
{UART2_TX, (M0)}, /* uart2_tx */ {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */
{HDQ_SIO, (M3)}, /* gpio_127 */ {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {RFBI_DATA14, (M4)}, /* KBD_COL7 */
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ {RFBI_DATA15, (M4)}, /* KBD_COL6 */
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ {GPIO6_182, (M6)}, /* GPIO6_182 */
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ {GPIO6_184, (M4)}, /* KBD_COL2 */
{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */
{MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */
{UART4_RX, (IEN | M0)}, /* uart4_rx */ {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */
{UART4_TX, (M0)}, /* uart4_tx */ {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */
{USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */
{USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/
{USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/
{USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */
{USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */
{USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */
{USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */
{USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */
{USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */
{USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */
{USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */
{USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */
{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */
{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */
{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */
{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */
{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */
{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */
{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */
{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */
{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */
{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */
{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */
{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */
{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */
{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */
{FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */
{FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {CAM_STROBE, (M0)}, /* CAM_STROBE */
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */
{SYS_NIRQ2, (M7)}, /* sys_nirq2 */ {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */
{SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */
{SYS_BOOT1, (M3)}, /* gpio_185 */ {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */
{SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */
{SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */
{SYS_BOOT4, (M3)}, /* gpio_188 */ {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */
{SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */
{DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */
{DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */
{DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */
{DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */
{DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */
{DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */
{DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */
{DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */
{DPM_EMU10, (IEN | M5)}, /* dispc2_de */ {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */
{DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */
{DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */
{DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */
{DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */
{DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */
{DPM_EMU16, (M3)}, /* gpio_27 */ {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */
{DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */
{DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */
{DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ {UART5_TX, (M0)}, /* UART5_TX */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ {UART5_RTS, (M0)}, /* UART5_RTS */
{I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */
{I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */
{MCSPI1_CLK, (M6)}, /* GPIO5_140 */
{MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */
{MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */
{MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */
{MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */
{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
{PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */
{PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */
{UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */
{UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */
{UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */
{UART6_RTS, (PTU | M0)}, /* UART6_RTS */
{UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */
{UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */
{USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
{USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
{USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
{USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
{USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
{I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
{I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
}; };
const struct pad_conf_entry wkup_padconf_array_non_essential[] = { const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
{PAD1_SIM_CLK, (M0)}, /* sim_clk */ /*
{PAD0_SIM_RESET, (M0)}, /* sim_reset */ * This pad keeps C2C Module always enabled.
{PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ * Putting this in safe mode do not cause the issue.
{PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ * C2C driver could enable this mux setting if needed.
{PAD1_FREF_XTAL_IN, (M0)}, /* # */ */
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */
{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */
{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */
{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */
{PAD0_FREF_CLK4_OUT, (M0)}, /* # */ {JTAG_RTCK, (M0)}, /* JTAG_RTCK */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ {JTAG_TDO, (M0)}, /* JTAG_TDO */
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */
{PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */
{PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */
{PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */
{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */
{PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */
{SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */
{SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */
{SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */
{SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */
{SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */
{SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */
{SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */
{SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */
{SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */
{SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */
{SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */
}; };
#endif /* _EVM4430_MUX_DATA_H */ #endif /* _EVM4430_MUX_DATA_H */