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Merge branch 'master' of git://git.denx.de/u-boot-mips

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This commit is contained in:
Wolfgang Denk 2011-05-10 22:34:24 +02:00
commit 8c65b8a937
14 changed files with 135 additions and 248 deletions
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2
arch/mips/config.mk
View File

@ -50,3 +50,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
PLATFORM_CPPFLAGS += -msoft-float PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections

2
arch/mips/cpu/mips32/Makefile
View File

@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).o
START = start.o START = start.o
SOBJS-y = cache.o SOBJS-y = cache.o
COBJS-y = cpu.o interrupts.o COBJS-y = cpu.o interrupts.o time.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

174
arch/mips/cpu/mips32/cache.S
View File

@ -51,75 +51,6 @@
.set pop .set pop
.endm .endm
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,9f ; \
move size,maxsize ; \
9:
#define _align(minaddr, maxaddr, linesize) \
.set noat ; \
subu AT,linesize,1 ; \
not AT ; \
and minaddr,AT ; \
addu maxaddr,-1 ; \
and maxaddr,AT ; \
.set at
/* general operations */
#define doop1(op1) \
cache op1,0(a0)
#define doop2(op1, op2) \
cache op1,0(a0) ; \
nop ; \
cache op2,0(a0)
/* specials for cache initialisation */
#define doop1lw(op1) \
lw zero,0(a0)
#define doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
#define doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
10: doop##tag##ops ; \
bne minaddr,maxaddr,10b ; \
add minaddr,linesize ; \
.set reorder
/* finally the cache operation macros */
#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
_mincache(n, cacheSize); \
blez n,11f ; \
addu n,kva ; \
_align(kva, n, cacheLineSize) ; \
_oploopn(kva, n, cacheLineSize, tag, ops) ; \
11:
#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
.macro f_fill64 dst, offset, val .macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
@ -145,8 +76,8 @@
* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
*/ */
LEAF(mips_init_icache) LEAF(mips_init_icache)
blez a1, 9f blez a1, 9f
mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO
/* clear tag to invalidate */ /* clear tag to invalidate */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
@ -163,15 +94,15 @@ LEAF(mips_init_icache)
1: cache_op Index_Store_Tag_I t0 1: cache_op Index_Store_Tag_I t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
9: jr ra 9: jr ra
END(mips_init_icache) END(mips_init_icache)
/* /*
* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
*/ */
LEAF(mips_init_dcache) LEAF(mips_init_dcache)
blez a1, 9f blez a1, 9f
mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO
/* clear all tags */ /* clear all tags */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
@ -188,25 +119,23 @@ LEAF(mips_init_dcache)
1: cache_op Index_Store_Tag_D t0 1: cache_op Index_Store_Tag_D t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
9: jr ra 9: jr ra
END(mips_init_dcache) END(mips_init_dcache)
/******************************************************************************* /*
* * mips_cache_reset - low level initialisation of the primary caches
* mips_cache_reset - low level initialisation of the primary caches *
* * This routine initialises the primary caches to ensure that they have good
* This routine initialises the primary caches to ensure that they * parity. It must be called by the ROM before any cached locations are used
* have good parity. It must be called by the ROM before any cached locations * to prevent the possibility of data with bad parity being written to memory.
* are used to prevent the possibility of data with bad parity being written to *
* memory. * To initialise the instruction cache it is essential that a source of data
* To initialise the instruction cache it is essential that a source of data * with good parity is available. This routine will initialise an area of
* with good parity is available. This routine * memory starting at location zero to be used as a source of parity.
* will initialise an area of memory starting at location zero to be used as *
* a source of parity. * RETURNS: N/A
* *
* RETURNS: N/A */
*
*/
NESTED(mips_cache_reset, 0, ra) NESTED(mips_cache_reset, 0, ra)
move RA, ra move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE li t2, CONFIG_SYS_ICACHE_SIZE
@ -254,13 +183,12 @@ NESTED(mips_cache_reset, 0, ra)
jr RA jr RA
END(mips_cache_reset) END(mips_cache_reset)
/******************************************************************************* /*
* * dcache_status - get cache status
* dcache_status - get cache status *
* * RETURNS: 0 - cache disabled; 1 - cache enabled
* RETURNS: 0 - cache disabled; 1 - cache enabled *
* */
*/
LEAF(dcache_status) LEAF(dcache_status)
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
li t1, CONF_CM_UNCACHED li t1, CONF_CM_UNCACHED
@ -271,13 +199,12 @@ LEAF(dcache_status)
2: jr ra 2: jr ra
END(dcache_status) END(dcache_status)
/******************************************************************************* /*
* * dcache_disable - disable cache
* dcache_disable - disable cache *
* * RETURNS: N/A
* RETURNS: N/A *
* */
*/
LEAF(dcache_disable) LEAF(dcache_disable)
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
li t1, -8 li t1, -8
@ -287,13 +214,12 @@ LEAF(dcache_disable)
jr ra jr ra
END(dcache_disable) END(dcache_disable)
/******************************************************************************* /*
* * dcache_enable - enable cache
* dcache_enable - enable cache *
* * RETURNS: N/A
* RETURNS: N/A *
* */
*/
LEAF(dcache_enable) LEAF(dcache_enable)
mfc0 t0, CP0_CONFIG mfc0 t0, CP0_CONFIG
ori t0, CONF_CM_CMASK ori t0, CONF_CM_CMASK
@ -302,27 +228,3 @@ LEAF(dcache_enable)
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
jr ra jr ra
END(dcache_enable) END(dcache_enable)
#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
* RETURNS: N/A
*
*/
# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
jr ra
.end mips_cache_lock
#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */

124
arch/mips/cpu/mips32/start.S
View File

@ -62,11 +62,11 @@
.globl _start .globl _start
.text .text
_start: _start:
RVECENT(reset,0) /* U-boot entry point */ RVECENT(reset,0) # U-boot entry point
RVECENT(reset,1) /* software reboot */ RVECENT(reset,1) # software reboot
#if defined(CONFIG_INCA_IP) #ifdef CONFIG_INCA_IP
.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
.word 0x00000000 /* phase of the flash */ .word 0x00000000 # booting phase of the flash
#else #else
RVECENT(romReserved,2) RVECENT(romReserved,2)
#endif #endif
@ -131,7 +131,7 @@ _start:
RVECENT(romReserved,61) RVECENT(romReserved,61)
RVECENT(romReserved,62) RVECENT(romReserved,62)
RVECENT(romReserved,63) RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */ XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
RVECENT(romReserved,65) RVECENT(romReserved,65)
RVECENT(romReserved,66) RVECENT(romReserved,66)
RVECENT(romReserved,67) RVECENT(romReserved,67)
@ -147,7 +147,7 @@ _start:
RVECENT(romReserved,77) RVECENT(romReserved,77)
RVECENT(romReserved,78) RVECENT(romReserved,78)
RVECENT(romReserved,79) RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */ XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
RVECENT(romReserved,81) RVECENT(romReserved,81)
RVECENT(romReserved,82) RVECENT(romReserved,82)
RVECENT(romReserved,83) RVECENT(romReserved,83)
@ -163,7 +163,7 @@ _start:
RVECENT(romReserved,93) RVECENT(romReserved,93)
RVECENT(romReserved,94) RVECENT(romReserved,94)
RVECENT(romReserved,95) RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */ XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
RVECENT(romReserved,97) RVECENT(romReserved,97)
RVECENT(romReserved,98) RVECENT(romReserved,98)
RVECENT(romReserved,99) RVECENT(romReserved,99)
@ -179,7 +179,7 @@ _start:
RVECENT(romReserved,109) RVECENT(romReserved,109)
RVECENT(romReserved,110) RVECENT(romReserved,110)
RVECENT(romReserved,111) RVECENT(romReserved,111)
XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */ XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
RVECENT(romReserved,113) RVECENT(romReserved,113)
RVECENT(romReserved,114) RVECENT(romReserved,114)
RVECENT(romReserved,115) RVECENT(romReserved,115)
@ -196,19 +196,19 @@ _start:
RVECENT(romReserved,126) RVECENT(romReserved,126)
RVECENT(romReserved,127) RVECENT(romReserved,127)
/* We hope there are no more reserved vectors! /*
* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400 * 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400 * so this is address R_VEC+0x400 == 0xbfc00400
*/ */
.align 4 .align 4
reset: reset:
/* Clear watch registers. /* Clear watch registers */
*/
mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI mtc0 zero, CP0_WATCHHI
/* WP(Watch Pending), SW0/1 should be cleared. */ /* WP(Watch Pending), SW0/1 should be cleared */
mtc0 zero, CP0_CAUSE mtc0 zero, CP0_CAUSE
setup_c0_status_reset setup_c0_status_reset
@ -217,54 +217,42 @@ reset:
mtc0 zero, CP0_COUNT mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE mtc0 zero, CP0_COMPARE
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) #ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* CONFIG0 register */ /* CONFIG0 register */
li t0, CONF_CM_UNCACHED li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ #endif
/* Initialize $gp. /* Initialize $gp */
*/
bal 1f bal 1f
nop nop
.word _gp .word _gp
1: 1:
lw gp, 0(ra) lw gp, 0(ra)
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) #ifndef CONFIG_SKIP_LOWLEVEL_INIT
/* Initialize any external memory. /* Initialize any external memory */
*/
la t9, lowlevel_init la t9, lowlevel_init
jalr t9 jalr t9
nop nop
/* Initialize caches... /* Initialize caches... */
*/
la t9, mips_cache_reset la t9, mips_cache_reset
jalr t9 jalr t9
nop nop
/* ... and enable them. /* ... and enable them */
*/
li t0, CONF_CM_CACHABLE_NONCOHERENT li t0, CONF_CM_CACHABLE_NONCOHERENT
mtc0 t0, CP0_CONFIG mtc0 t0, CP0_CONFIG
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
/* Set up temporary stack.
*/
#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
li a0, CONFIG_SYS_INIT_SP_OFFSET
la t9, mips_cache_lock
jalr t9
nop
#endif #endif
/* Set up temporary stack */
li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la sp, 0(t0) la sp, 0(t0)
la t9, board_init_f la t9, board_init_f
jr t9 jr t9
nop nop
/* /*
* void relocate_code (addr_sp, gd, addr_moni) * void relocate_code (addr_sp, gd, addr_moni)
@ -279,13 +267,13 @@ reset:
.globl relocate_code .globl relocate_code
.ent relocate_code .ent relocate_code
relocate_code: relocate_code:
move sp, a0 /* Set new stack pointer */ move sp, a0 # set new stack pointer
li t0, CONFIG_SYS_MONITOR_BASE li t0, CONFIG_SYS_MONITOR_BASE
la t3, in_ram la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */ lw t2, -12(t3) # t2 <-- uboot_end_data
move t1, a2 move t1, a2
move s2, a2 /* s2 <-- destination address */ move s2, a2 # s2 <-- destination address
/* /*
* Fix $gp: * Fix $gp:
@ -294,8 +282,8 @@ relocate_code:
*/ */
move t6, gp move t6, gp
sub gp, CONFIG_SYS_MONITOR_BASE sub gp, CONFIG_SYS_MONITOR_BASE
add gp, a2 /* gp now adjusted */ add gp, a2 # gp now adjusted
sub s1, gp, t6 /* s1 <-- relocation offset */ sub s1, gp, t6 # s1 <-- relocation offset
/* /*
* t0 = source address * t0 = source address
@ -306,30 +294,28 @@ relocate_code:
/* /*
* Save destination address and size for later usage in flush_cache() * Save destination address and size for later usage in flush_cache()
*/ */
move s0, a1 /* save gd in s0 */ move s0, a1 # save gd in s0
move a0, t1 /* a0 <-- destination addr */ move a0, t1 # a0 <-- destination addr
sub a1, t2, t0 /* a1 <-- size */ sub a1, t2, t0 # a1 <-- size
1: 1:
lw t3, 0(t0) lw t3, 0(t0)
sw t3, 0(t1) sw t3, 0(t1)
addu t0, 4 addu t0, 4
ble t0, t2, 1b ble t0, t2, 1b
addu t1, 4 /* delay slot */ addu t1, 4
/* If caches were enabled, we would have to flush them here. /* If caches were enabled, we would have to flush them here. */
*/
/* a0 & a1 are already set up for flush_cache(start, size) */ /* a0 & a1 are already set up for flush_cache(start, size) */
la t9, flush_cache la t9, flush_cache
jalr t9 jalr t9
nop nop
/* Jump to where we've relocated ourselves. /* Jump to where we've relocated ourselves */
*/
addi t0, s2, in_ram - _start addi t0, s2, in_ram - _start
jr t0 jr t0
nop nop
.word _gp .word _gp
.word _GLOBAL_OFFSET_TABLE_ .word _GLOBAL_OFFSET_TABLE_
@ -344,45 +330,43 @@ in_ram:
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation. * generated by GNU ld. Skip these reserved entries from relocation.
*/ */
lw t3, -4(t0) /* t3 <-- num_got_entries */ lw t3, -4(t0) # t3 <-- num_got_entries
lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
lw t5, -20(t0) /* t5 <-- _gp */ lw t5, -20(t0) # t5 <-- _gp
sub t4, t5 /* compute offset*/ sub t4, t5 # compute offset
add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ add t4, t4, gp # t4 now holds relocated _G_O_T_
addi t4, t4, 8 /* Skipping first two entries. */ addi t4, t4, 8 # skipping first two entries
li t2, 2 li t2, 2
1: 1:
lw t1, 0(t4) lw t1, 0(t4)
beqz t1, 2f beqz t1, 2f
add t1, s1 add t1, s1
sw t1, 0(t4) sw t1, 0(t4)
2: 2:
addi t2, 1 addi t2, 1
blt t2, t3, 1b blt t2, t3, 1b
addi t4, 4 /* delay slot */ addi t4, 4
/* Clear BSS. /* Clear BSS */
*/ lw t1, -12(t0) # t1 <-- uboot_end_data
lw t1, -12(t0) /* t1 <-- uboot_end_data */ lw t2, -8(t0) # t2 <-- uboot_end
lw t2, -8(t0) /* t2 <-- uboot_end */ add t1, s1 # adjust pointers
add t1, s1 /* adjust pointers */
add t2, s1 add t2, s1
sub t1, 4 sub t1, 4
1: 1:
addi t1, 4 addi t1, 4
bltl t1, t2, 1b bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */ sw zero, 0(t1)
move a0, s0 /* a0 <-- gd */ move a0, s0 # a0 <-- gd
la t9, board_init_r la t9, board_init_r
jr t9 jr t9
move a1, s2 /* delay slot */ move a1, s2
.end relocate_code .end relocate_code
/* Exception handlers. /* Exception handlers */
*/
romReserved: romReserved:
b romReserved b romReserved

0
arch/mips/lib/time.c → arch/mips/cpu/mips32/time.c
View File

1
arch/mips/lib/Makefile
View File

@ -33,7 +33,6 @@ COBJS-y += bootm_qemu_mips.o
else else
COBJS-y += bootm.o COBJS-y += bootm.o
endif endif
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

10
board/dbau1x00/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -52,7 +52,7 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
.u_boot_cmd : { .u_boot_cmd : {
__u_boot_cmd_start = .; __u_boot_cmd_start = .;
@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
board/gth2/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -52,7 +52,7 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
.u_boot_cmd : { .u_boot_cmd : {
__u_boot_cmd_start = .; __u_boot_cmd_start = .;
@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
board/incaip/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -52,7 +52,7 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
.u_boot_cmd : { .u_boot_cmd : {
__u_boot_cmd_start = .; __u_boot_cmd_start = .;
@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
board/micronas/vct/u-boot.lds
View File

@ -31,14 +31,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -50,7 +50,7 @@ SECTIONS
} }
. = ALIGN(4); . = ALIGN(4);
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
. = ALIGN(4); . = ALIGN(4);
.u_boot_cmd : { .u_boot_cmd : {
@ -64,8 +64,8 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
. = ALIGN(4); . = ALIGN(4);
.bss (NOLOAD) : { *(.bss) } .bss (NOLOAD) : { *(.bss*) }
uboot_end = .; uboot_end = .;
} }

10
board/pb1x00/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -52,7 +52,7 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
.u_boot_cmd : { .u_boot_cmd : {
__u_boot_cmd_start = .; __u_boot_cmd_start = .;
@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
board/qemu-mips/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) +0x7ff0; _gp = ALIGN(16) +0x7ff0;
@ -53,7 +53,7 @@ SECTIONS
} }
. = ALIGN(4); . = ALIGN(4);
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
. = .; . = .;
.u_boot_cmd : { .u_boot_cmd : {
@ -66,7 +66,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss : { *(.sbss) } .sbss : { *(.sbss*) }
.bss : { *(.bss) . = ALIGN(4); } .bss : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
board/tb0229/u-boot.lds
View File

@ -34,14 +34,14 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -52,7 +52,7 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
.u_boot_cmd : { .u_boot_cmd : {
__u_boot_cmd_start = .; __u_boot_cmd_start = .;
@ -64,7 +64,7 @@ SECTIONS
num_got_entries = (__got_end - __got_start) >> 2; num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4); . = ALIGN(4);
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
uboot_end = .; uboot_end = .;
} }

10
examples/standalone/mips.lds
View File

@ -30,14 +30,14 @@ SECTIONS
{ {
.text : .text :
{ {
*(.text) *(.text*)
} }
. = ALIGN(4); . = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4); . = ALIGN(4);
.data : { *(.data) } .data : { *(.data*) }
. = .; . = .;
_gp = ALIGN(16) + 0x7ff0; _gp = ALIGN(16) + 0x7ff0;
@ -48,12 +48,12 @@ SECTIONS
__got_end = .; __got_end = .;
} }
.sdata : { *(.sdata) } .sdata : { *(.sdata*) }
. = ALIGN(4); . = ALIGN(4);
__bss_start = .; __bss_start = .;
.sbss (NOLOAD) : { *(.sbss) } .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); } .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
_end = .; _end = .;
} }