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85xx/p1_p2rdb: Fix crash while configuring 32 bit DDR i/f for P1020RDB.

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The data being modified was in NOR flash which caused the crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal 2009-10-27 09:26:55 +05:30 committed by Kumar Gala
parent 3e303f748c
commit 924024c396
1 changed files with 8 additions and 8 deletions
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16
board/freescale/p1_p2_rdb/ddr.c
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@ -206,7 +206,7 @@ phys_size_t fixed_sdram (void)
{ {
sys_info_t sysinfo; sys_info_t sysinfo;
char buf[32]; char buf[32];
fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL; fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size; size_t ddr_size;
struct cpu_type *cpu; struct cpu_type *cpu;
@ -215,13 +215,13 @@ phys_size_t fixed_sdram (void)
strmhz(buf, sysinfo.freqDDRBus)); strmhz(buf, sysinfo.freqDDRBus));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ) if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
ddr_cfg_regs = &ddr_cfg_regs_400; memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
ddr_cfg_regs = &ddr_cfg_regs_533; memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
ddr_cfg_regs = &ddr_cfg_regs_667; memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
ddr_cfg_regs = &ddr_cfg_regs_800; memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else else
panic("Unsupported DDR data rate %s MT/s data rate\n", panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus)); strmhz(buf, sysinfo.freqDDRBus));
@ -230,14 +230,14 @@ phys_size_t fixed_sdram (void)
/* P1020 and it's derivatives support max 32bit DDR width */ /* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
ddr_cfg_regs->cs[0].bnds = 0x0000001F; ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
} }
else else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0); fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
return ddr_size; return ddr_size;
} }