omap3: remove typedefs for configuration structs

Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>

board/omap3/beagle/beagle.c

@@ -103,8 +103,8 @@ void beagle_identify(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
 	twl4030_power_init();
 	twl4030_led_init();

board/omap3/evm/evm.c

@@ -92,9 +92,9 @@ void set_muxconf_regs(void)
  */
 static void setup_net_chip(void)
 {
-	gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
+	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
-	gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
+	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
-	ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
 	writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1);

board/omap3/pandora/pandora.c

@@ -60,10 +60,10 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
+	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
-	gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
+	struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
 	twl4030_power_init();
 	twl4030_led_init();

board/omap3/zoom2/zoom2.c

@@ -123,7 +123,7 @@ void zoom2_identify(void)
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
+	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
 	u32 *gpmc_config;
 
 	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */

cpu/arm_cortexa8/omap3/board.c

@@ -59,11 +59,11 @@ static inline void delay(unsigned long loops)
  *****************************************************************************/
 void secure_unlock_mem(void)
 {
-	pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
+	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
-	pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
+	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
-	pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
+	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
-	pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
+	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
-	sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
+	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 
 	/* Protection Module Register Target APE (PM_RT) */
 	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
@@ -234,7 +234,7 @@ void s_init(void)
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
  *****************************************************************************/
-void wait_for_command_complete(watchdog_t *wd_base)
+void wait_for_command_complete(struct watchdog *wd_base)
 {
 	int pending = 1;
 	do {
@@ -248,8 +248,8 @@ void wait_for_command_complete(watchdog_t *wd_base)
  *****************************************************************************/
 void watchdog_init(void)
 {
-	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
+	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/*
 	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is

cpu/arm_cortexa8/omap3/clock.c

@@ -41,10 +41,10 @@
 u32 get_osc_clk_speed(void)
 {
 	u32 start, cstart, cend, cdiff, val;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
-	gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
+	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
-	s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
+	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
 
 	val = readl(&prm_base->clksrc_ctrl);
 
@@ -133,8 +133,8 @@ void prcm_init(void)
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
 	u32 clk_index, sil_index = 0;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	dpll_param *dpll_param_p;
 
 	f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
@@ -341,7 +341,7 @@ void prcm_init(void)
  *****************************************************************************/
 void per_clocks_enable(void)
 {
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/* Enable GP2 timer. */
 	sr32(&prcm_base->clksel_per, 0, 1, 0x1);	/* GPT2 = sys clk */

cpu/arm_cortexa8/omap3/mem.c

@@ -51,7 +51,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG6, 0
 };
 
-gpmc_t *gpmc_cfg_base;
+struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_ENV_IS_IN_NAND)
 #define GPMC_CS 0
@@ -79,7 +79,7 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
 
 #endif
 
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 
 /**************************************************************************
  * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
@@ -146,12 +146,12 @@ void sdrc_init(void)
 
 void do_sdrc_init(u32 cs, u32 early)
 {
-	sdrc_actim_t *sdrc_actim_base;
+	struct sdrc_actim *sdrc_actim_base;
 
 	if(cs)
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 	else
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 
 	if (early) {
 		/* reset sdrc controller */
@@ -219,7 +219,7 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	u32 *gpmc_config = NULL;
-	gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+	struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 	u32 base = 0;
 	u32 size = 0;
 	u32 f_off = CONFIG_SYS_MONITOR_LEN;
@@ -243,7 +243,7 @@ void gpmc_init(void)
 
 #if defined(CONFIG_CMD_NAND)	/* CS 0 */
 	gpmc_config = gpmc_m_nand;
-	gpmc_cfg_base = gpmc_base;
+	gpmc_cfg = gpmc_base;
 
 	base = PISMO1_NAND_BASE;
 	size = PISMO1_NAND_SIZE;

cpu/arm_cortexa8/omap3/sys_info.c

@@ -32,9 +32,9 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
 				"2.0",
@@ -47,7 +47,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
  *****************************************************************/
 void dieid_num_r(void)
 {
-	ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 	char *uid_s, die_id[34];
 	u32 id[4];
 
@@ -82,7 +82,7 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
-	ctrl_id_t *id_base;
+	struct ctrl_id *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4
@@ -93,7 +93,7 @@ u32 get_cpu_rev(void)
 		return CPU_3XX_ES10;
 	else {
 		/* Decode the IDs on > ES1.0 */
-		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 
 		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
 

cpu/arm_cortexa8/omap3/timer.c

@@ -37,7 +37,7 @@
 
 static ulong timestamp;
 static ulong lastinc;
-static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * Nothing really to do with interrupts, just starts up a counter.

drivers/mtd/nand/omap_gpmc.c

@@ -30,7 +30,7 @@
 #include <nand.h>
 
 static uint8_t cs;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
 
 /*

include/asm-arm/arch-omap3/cpu.h

@@ -28,7 +28,7 @@
 /* Register offsets of common modules */
 /* Control */
 #ifndef __ASSEMBLY__
-typedef struct ctrl {
+struct ctrl {
 	unsigned char res1[0xC0];
 	unsigned short gpmc_nadv_ale;	/* 0xC0 */
 	unsigned short gpmc_noe;	/* 0xC2 */
@@ -49,7 +49,7 @@ typedef struct ctrl {
 	unsigned int randkey_3;		/* 0x324 */
 	unsigned char res5[0x124];
 	unsigned int ctrl_omap_stat;	/* 0x44C */
-} ctrl_t;
+};
 #else /* __ASSEMBLY__ */
 #define CONTROL_STATUS		0x2F0
 #endif /* __ASSEMBLY__ */
@@ -61,7 +61,7 @@ typedef struct ctrl {
 #define OMAP3530		0x0c00
 
 #ifndef __ASSEMBLY__
-typedef struct ctrl_id {
+struct ctrl_id {
 	unsigned char res1[0x4];
 	unsigned int idcode;		/* 0x04 */
 	unsigned int prod_id;		/* 0x08 */
@@ -70,7 +70,7 @@ typedef struct ctrl_id {
 	unsigned int die_id_1;		/* 0x1C */
 	unsigned int die_id_2;		/* 0x20 */
 	unsigned int die_id_3;		/* 0x24 */
-} ctrl_id_t;
+};
 #endif /* __ASSEMBLY__ */
 
 /* device type */
@@ -99,7 +99,7 @@ struct gpmc_cs {
 	unsigned char res[8];		/* blow up to 0x30 byte */
 };
 
-typedef struct gpmc {
+struct gpmc {
 	unsigned char res1[0x10];
 	unsigned int sysconfig;		/* 0x10 */
 	unsigned char res2[0x4];
@@ -125,7 +125,7 @@ typedef struct gpmc {
 	unsigned int ecc7_result;	/* 0x218 */
 	unsigned int ecc8_result;	/* 0x21C */
 	unsigned int ecc9_result;	/* 0x220 */
-} gpmc_t;
+};
 #else /* __ASSEMBLY__ */
 #define GPMC_CONFIG1		0x00
 #define GPMC_CONFIG2		0x04
@@ -151,21 +151,21 @@ typedef struct gpmc {
 						/* (actual size small port) */
 /* SMS */
 #ifndef __ASSEMBLY__
-typedef struct sms {
+struct sms {
 	unsigned char res1[0x10];
 	unsigned int sysconfig;		/* 0x10 */
 	unsigned char res2[0x34];
 	unsigned int rg_att0;		/* 0x48 */
 	unsigned char res3[0x84];
 	unsigned int class_arb0;	/* 0xD0 */
-} sms_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define BURSTCOMPLETE_GROUP7	(0x1 << 31)
 
 /* SDRC */
 #ifndef __ASSEMBLY__
-typedef struct sdrc_cs {
+struct sdrc_cs {
 	unsigned int mcfg;		/* 0x80 || 0xB0 */
 	unsigned int mr;		/* 0x84 || 0xB4 */
 	unsigned char res1[0x4];
@@ -174,14 +174,14 @@ typedef struct sdrc_cs {
 	unsigned int rfr_ctrl;		/* 0x84 || 0xD4 */
 	unsigned int manual;		/* 0xA8 || 0xD8 */
 	unsigned char res3[0x4];
-} sdrc_cs_t;
+};
 
-typedef struct sdrc_actim {
+struct sdrc_actim {
 	unsigned int ctrla;		/* 0x9C || 0xC4 */
 	unsigned int ctrlb;		/* 0xA0 || 0xC8 */
-} sdrc_actim_t;
+};
 
-typedef struct sdrc {
+struct sdrc {
 	unsigned char res1[0x10];
 	unsigned int sysconfig;		/* 0x10 */
 	unsigned int status;		/* 0x14 */
@@ -195,8 +195,8 @@ typedef struct sdrc {
 	unsigned int dllb_status;	/* 0x6C */
 	unsigned int power;		/* 0x70 */
 	unsigned char res4[0xC];
-	sdrc_cs_t cs[2];		/* 0x80 || 0xB0 */
+	struct sdrc_cs cs[2];		/* 0x80 || 0xB0 */
-} sdrc_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define DLLPHASE_90		(0x1 << 1)
@@ -240,7 +240,7 @@ typedef struct sdrc {
 /* timer regs offsets (32 bit regs) */
 
 #ifndef __ASSEMBLY__
-typedef struct gptimer {
+struct gptimer {
 	unsigned int tidr;	/* 0x00 r */
 	unsigned char res[0xc];
 	unsigned int tiocp_cfg;	/* 0x10 rw */
@@ -257,7 +257,7 @@ typedef struct gptimer {
 	unsigned int tcar1;	/* 0x3c r */
 	unsigned int tcicr;	/* 0x40 rw */
 	unsigned int tcar2;	/* 0x44 r */
-} gptimer_t;
+};
 #endif /* __ASSEMBLY__ */
 
 /* enable sys_clk NO-prescale /1 */
@@ -265,12 +265,12 @@ typedef struct gptimer {
 
 /* Watchdog */
 #ifndef __ASSEMBLY__
-typedef struct watchdog {
+struct watchdog {
 	unsigned char res1[0x34];
 	unsigned int wwps;	/* 0x34 r */
 	unsigned char res2[0x10];
 	unsigned int wspr;	/* 0x48 rw */
-} watchdog_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define WD_UNLOCK1		0xAAAA
@@ -280,7 +280,7 @@ typedef struct watchdog {
 #define PRCM_BASE		0x48004000
 
 #ifndef __ASSEMBLY__
-typedef struct prcm {
+struct prcm {
 	unsigned int fclken_iva2;	/* 0x00 */
 	unsigned int clken_pll_iva2;	/* 0x04 */
 	unsigned char res1[0x1c];
@@ -344,7 +344,7 @@ typedef struct prcm {
 	unsigned int clksel_per;	/* 0x1040 */
 	unsigned char res28[0xfc];
 	unsigned int clksel1_emu;	/* 0x1140 */
-} prcm_t;
+};
 #else /* __ASSEMBLY__ */
 #define CM_CLKSEL_CORE		0x48004a40
 #define CM_CLKSEL_GFX		0x48004b40
@@ -357,14 +357,14 @@ typedef struct prcm {
 #define PRM_BASE		0x48306000
 
 #ifndef __ASSEMBLY__
-typedef struct prm {
+struct prm {
 	unsigned char res1[0xd40];
 	unsigned int clksel;		/* 0xd40 */
 	unsigned char res2[0x50c];
 	unsigned int rstctrl;		/* 0x1250 */
 	unsigned char res3[0x1c];
 	unsigned int clksrc_ctrl;	/* 0x1270 */
-} prm_t;
+};
 #else /* __ASSEMBLY__ */
 #define PRM_RSTCTRL		0x48307250
 #endif /* __ASSEMBLY__ */
@@ -400,7 +400,7 @@ typedef struct prm {
 #define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
 
 #ifndef __ASSEMBLY__
-typedef struct pm {
+struct pm {
 	unsigned char res1[0x48];
 	unsigned int req_info_permission_0;	/* 0x48 */
 	unsigned char res2[0x4];
@@ -413,7 +413,7 @@ typedef struct pm {
 	unsigned int req_info_permission_1;	/* 0x68 */
 	unsigned char res6[0x14];
 	unsigned int addr_match_2;		/* 0x80 */
-} pm_t;
+};
 #endif /*__ASSEMBLY__ */
 
 /* Permission values for registers -Full fledged permissions to all */

include/asm-arm/arch-omap3/mem.h

@@ -29,12 +29,12 @@
 #define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
 
 #ifndef __ASSEMBLY__
-typedef enum {
+enum {
 	STACKED = 0,
 	IP_DDR = 1,
 	COMBO_DDR = 2,
 	IP_SDR = 3,
-} mem_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define EARLY_INIT	1

include/asm-arm/arch-omap3/omap3.h

@@ -79,10 +79,10 @@
 
 #ifndef __ASSEMBLY__
 
-typedef struct s32ktimer {
+struct s32ktimer {
 	unsigned char res[0x10];
 	unsigned int s32k_cr;		/* 0x10 */
-} s32ktimer_t;
+};
 
 #endif /* __ASSEMBLY__ */
 
@@ -95,14 +95,14 @@ typedef struct s32ktimer {
 #define OMAP34XX_GPIO6_BASE		0x49058000
 
 #ifndef __ASSEMBLY__
-typedef struct gpio {
+struct gpio {
 	unsigned char res1[0x34];
 	unsigned int oe;		/* 0x34 */
 	unsigned int datain;		/* 0x38 */
 	unsigned char res2[0x54];
 	unsigned int cleardataout;	/* 0x90 */
 	unsigned int setdataout;	/* 0x94 */
-} gpio_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define GPIO0				(0x1 << 0)

include/configs/omap3_beagle.h

@@ -300,7 +300,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_evm.h

@@ -292,7 +292,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_overo.h

@@ -285,7 +285,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_pandora.h

@@ -289,7 +289,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_zoom1.h

@@ -297,7 +297,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

include/configs/omap3_zoom2.h

@@ -252,7 +252,7 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;