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DM9000: Some minor code cleanups

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Some lines of the U-boot DM9000x driver are longer than 80 characters, or
need some other minor cleanup.

Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Remy Bohmer 2008-06-03 15:26:26 +02:00 committed by Ben Warren
parent 850ba7555d
commit 98291e2e68
1 changed files with 26 additions and 15 deletions
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41
drivers/net/dm9000x.c
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@ -51,6 +51,7 @@ v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
for DM9000A. for DM9000A.
- Adapted reset procedure to match DM9000 application - Adapted reset procedure to match DM9000 application
notes (i.e. double reset) notes (i.e. double reset)
- some minor code cleanups
These changes are tested with DM9000{A,EP,E} together These changes are tested with DM9000{A,EP,E} together
with a 200MHz Atmel AT91SAM92161 core with a 200MHz Atmel AT91SAM92161 core
@ -115,7 +116,7 @@ typedef struct board_info {
void (*outblk)(void *data_ptr, int count); void (*outblk)(void *data_ptr, int count);
void (*inblk)(void *data_ptr, int count); void (*inblk)(void *data_ptr, int count);
void (*rx_status)(u16 *RxStatus, u16 *RxLen); void (*rx_status)(u16 *RxStatus, u16 *RxLen);
} board_info_t; } board_info_t;
static board_info_t dm9000_info; static board_info_t dm9000_info;
/* For module input parameter */ /* For module input parameter */
@ -454,15 +455,22 @@ eth_init(bd_t * bd)
/* Set PHY */ /* Set PHY */
set_PHY_mode(); set_PHY_mode();
/* Program operating register */ /* Program operating register, only intern phy supported by now */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ DM9000_iow(DM9000_NCR, 0x0);
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ /* TX Polling clear */
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ DM9000_iow(DM9000_TCR, 0);
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ /* Less 3Kb, 200us */
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_BPTR, 0x3f);
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ /* Flow Control : High/Low Water */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ /* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_FCR, 0x0);
/* Special Mode */
DM9000_iow(DM9000_SMCR, 0);
/* clear TX status */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
/* Clear interrupt status */
DM9000_iow(DM9000_ISR, 0x0f);
/* Set Node address */ /* Set Node address */
for (i = 0; i < 6; i++) for (i = 0; i < 6; i++)
@ -496,8 +504,11 @@ eth_init(bd_t * bd)
DM9000_DBG("\n"); DM9000_DBG("\n");
/* Activate DM9000 */ /* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ /* RX enable */
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
/* Enable TX/RX interrupt mask */
DM9000_iow(DM9000_IMR, IMR_PAR);
i = 0; i = 0;
while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
udelay(1000); udelay(1000);
@ -720,7 +731,7 @@ phy_read(int reg)
/* Fill the phyxcer register into REG_0C */ /* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
udelay(100); /* Wait read complete */ udelay(100); /* Wait read complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
@ -743,8 +754,8 @@ phy_write(int reg, u16 value)
DM9000_iow(DM9000_EPDRL, (value & 0xff)); DM9000_iow(DM9000_EPDRL, (value & 0xff));
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
udelay(500); /* Wait write complete */ udelay(500); /* Wait write complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value); DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
} }
#endif /* CONFIG_DRIVER_DM9000 */ #endif /* CONFIG_DRIVER_DM9000 */