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ppc4xx: More cleanup for esd's LCD code

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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs 2008-01-02 12:05:14 +01:00 committed by Stefan Roese
parent fe9c26b330
commit 9ac6b6f3d3
1 changed files with 18 additions and 20 deletions
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28
board/esd/common/lcd.c
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@ -37,41 +37,41 @@ int lcd_depth;
unsigned char *glob_lcd_reg; unsigned char *glob_lcd_reg;
unsigned char *glob_lcd_mem; unsigned char *glob_lcd_mem;
#ifdef CFG_LCD_ENDIAN #if defined(CFG_LCD_ENDIAN)
void lcd_setup(int lcd, int config) void lcd_setup(int lcd, int config)
{ {
if (lcd == 0) { if (lcd == 0) {
/* /*
* Set endianess and reset lcd controller 0 (small) * Set endianess and reset lcd controller 0 (small)
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
udelay(10); /* wait 10us */ udelay(10); /* wait 10us */
if (config == 1) if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
else else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
udelay(10); /* wait 10us */ udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
} else { } else {
/* /*
* Set endianess and reset lcd controller 1 (big) * Set endianess and reset lcd controller 1 (big)
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
udelay(10); /* wait 10us */ udelay(10); /* wait 10us */
if (config == 1) if (config == 1)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
else else
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
udelay(10); /* wait 10us */ udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
} }
/* /*
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
*/ */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
} }
#endif /* #ifdef CFG_LCD_ENDIAN */ #endif /* CFG_LCD_ENDIAN */
void lcd_bmp(uchar *logo_bmp) void lcd_bmp(uchar *logo_bmp)
@ -93,7 +93,6 @@ void lcd_bmp(uchar *logo_bmp)
* Check for bmp mark 'BM' * Check for bmp mark 'BM'
*/ */
if (*(ushort *)logo_bmp != 0x424d) { if (*(ushort *)logo_bmp != 0x424d) {
/* /*
* Decompress bmp image * Decompress bmp image
*/ */
@ -202,11 +201,10 @@ void lcd_bmp(uchar *logo_bmp)
} }
} }
} else { } else {
for (x=0; x<line_size; x++) { for (x = 0; x < line_size; x++)
*ptr++ = *bmp++; *ptr++ = *bmp++;
} }
} }
}
if ((dst != NULL) && (dst != (uchar *)logo_bmp)) if ((dst != NULL) && (dst != (uchar *)logo_bmp))
free(dst); free(dst);
@ -296,7 +294,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
lcd_bmp(logo_bmp); lcd_bmp(logo_bmp);
} }
#ifdef CONFIG_VIDEO_SM501 #if defined(CONFIG_VIDEO_SM501)
int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
ulong addr; ulong addr;