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Coding style cleanup. Update CHANGELOG.

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Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2007-08-06 02:17:36 +02:00
parent 221838cc7e
commit 9c7e4b0621
16 changed files with 6441 additions and 6403 deletions
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61
CHANGELOG
View File

@ -1,3 +1,64 @@
commit 221838cc7eb178370ff62aa05920a582e12ac322
Author: Jason Jin <Jason.jin@freescale.com>
Date: Tue Jul 10 09:03:22 2007 +0800
Remove the bios emulator from MAI board.
The bios emulator in the MAI board can not pass compile
and have a lot of crap in it. remove it and will have a
clean and small bios emulator in the drivers directory
which can be uesed for every board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit 5618332409bb96f4448d1712899369fc80c0b489
Author: Jason Jin <Jason.jin@freescale.com>
Date: Fri Jul 13 12:14:59 2007 +0800
Fix some compile issues for MAI board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit 0f460a1ee148b648ee242c3157650287d4296260
Author: Jason Jin <Jason.jin@freescale.com>
Date: Fri Jul 13 12:14:58 2007 +0800
Configurations for ATI video card BIOS emulator
This patch add definition of the BIOS emulator and the ATI framebuffer
driver for MPC8641HPCN board.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
commit ece92f85053b8df613edcf05b26a416cbc3d629c
Author: Jason Jin <Jason.jin@freescale.com>
Date: Fri Jul 6 08:34:56 2007 +0800
This is a BIOS emulator, porting from SciTech for u-boot, mainly for
ATI video card BIOS. and can be used for x86 code emulation by some
modifications.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit 5072188acabde3178fac7f5a597150e6e74fd40c
Author: Jason Jin <Jason.jin@freescale.com>
Date: Fri Jul 6 08:33:33 2007 +0800
This is a framebuffer driver for ATI video card, can work for PCI9200,
X300, X700, X800 ATI video cards.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
commit 5728be389e65fd47f34b33c2596271eb4db751ae
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Aug 6 01:01:49 2007 +0200
Coding style cleanup. Update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 8092fef4c29b395958bb649647da7e3775731517 commit 8092fef4c29b395958bb649647da7e3775731517
Author: Martin Krause <Martin.Krause@tqs.de> Author: Martin Krause <Martin.Krause@tqs.de>
Date: Tue Dec 12 14:26:01 2006 +0100 Date: Tue Dec 12 14:26:01 2006 +0100

1
drivers/ati_ids.h
View File

@ -209,4 +209,3 @@
#define PCI_CHIP_R423_5D57 0x5D57 #define PCI_CHIP_R423_5D57 0x5D57
#define PCI_CHIP_RS350_7834 0x7834 #define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835 #define PCI_CHIP_RS350_7835 0x7835

19
drivers/ati_radeon_fb.h
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@ -5,7 +5,6 @@
* Most of the definitions here are adapted right from XFree86 * * Most of the definitions here are adapted right from XFree86 *
***************************************************************/ ***************************************************************/
/* /*
* Chip families. Must fit in the low 16 bits of a long word * Chip families. Must fit in the low 16 bits of a long word
*/ */
@ -38,14 +37,12 @@ enum radeon_family {
((rinfo)->family == CHIP_FAMILY_RV280) || \ ((rinfo)->family == CHIP_FAMILY_RV280) || \
((rinfo)->family == CHIP_FAMILY_RS300)) ((rinfo)->family == CHIP_FAMILY_RS300))
#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
((rinfo)->family == CHIP_FAMILY_RV350) || \ ((rinfo)->family == CHIP_FAMILY_RV350) || \
((rinfo)->family == CHIP_FAMILY_R350) || \ ((rinfo)->family == CHIP_FAMILY_R350) || \
((rinfo)->family == CHIP_FAMILY_RV380) || \ ((rinfo)->family == CHIP_FAMILY_RV380) || \
((rinfo)->family == CHIP_FAMILY_R420)) ((rinfo)->family == CHIP_FAMILY_R420))
struct radeonfb_info { struct radeonfb_info {
char name[20]; char name[20];
@ -86,7 +83,6 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
/* /*
* 2D Engine helper routines * 2D Engine helper routines
*/ */
@ -106,7 +102,6 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
printf("radeonfb: Flush Timeout !\n"); printf("radeonfb: Flush Timeout !\n");
} }
static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{ {
int i; int i;
@ -119,7 +114,6 @@ static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
printf("radeonfb: FIFO Timeout !\n"); printf("radeonfb: FIFO Timeout !\n");
} }
static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{ {
int i; int i;
@ -137,7 +131,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
printf("radeonfb: Idle Timeout !\n"); printf("radeonfb: Idle Timeout !\n");
} }
#define radeon_engine_idle() _radeon_engine_idle(rinfo) #define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
@ -255,9 +248,9 @@ static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
u32 data; u32 data;
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
//radeon_pll_errata_after_index(rinfo); /* radeon_pll_errata_after_index(rinfo); */
data = INREG(CLOCK_CNTL_DATA); data = INREG(CLOCK_CNTL_DATA);
//radeon_pll_errata_after_data(rinfo); /* radeon_pll_errata_after_data(rinfo); */
return data; return data;
} }
@ -266,12 +259,11 @@ static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
{ {
OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
//radeon_pll_errata_after_index(rinfo); /* radeon_pll_errata_after_index(rinfo); */
OUTREG(CLOCK_CNTL_DATA, val); OUTREG(CLOCK_CNTL_DATA, val);
//radeon_pll_errata_after_data(rinfo); /* radeon_pll_errata_after_data(rinfo); */
} }
static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask) u32 val, u32 mask)
{ {
@ -283,11 +275,8 @@ static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
__OUTPLL(rinfo, index, tmp); __OUTPLL(rinfo, index, tmp);
} }
#define INPLL(addr) __INPLL(rinfo, addr) #define INPLL(addr) __INPLL(rinfo, addr)
#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) #define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
#endif #endif

29
drivers/bios_emulator/besys.c
View File

@ -251,8 +251,7 @@ hardware does not support mapping the VGA I/O and memory (such as some
PowerPC systems), we emulate the VGA so that the BIOS will still be able to PowerPC systems), we emulate the VGA so that the BIOS will still be able to
set NonVGA display modes such as on ATI hardware. set NonVGA display modes such as on ATI hardware.
****************************************************************************/ ****************************************************************************/
static u8 VGA_inpb( static u8 VGA_inpb (const int port)
const int port)
{ {
u8 val = 0xff; u8 val = 0xff;
@ -263,11 +262,10 @@ static u8 VGA_inpb(
of an internal flip flop in the hardware. Hence we have of an internal flip flop in the hardware. Hence we have
to emulate that functionality in here. */ to emulate that functionality in here. */
if (_BE_env.flipFlop3C0 == 0) { if (_BE_env.flipFlop3C0 == 0) {
/* Access 3C0 as index register*/ /* Access 3C0 as index register */
val = _BE_env.emu3C0; val = _BE_env.emu3C0;
} } else {
else { /* Access 3C0 as data register */
/* Access 3C0 as data register*/
if (_BE_env.emu3C0 < ATT_C) if (_BE_env.emu3C0 < ATT_C)
val = _BE_env.emu3C1[_BE_env.emu3C0]; val = _BE_env.emu3C1[_BE_env.emu3C0];
} }
@ -328,22 +326,19 @@ Performs an emulated write to one of the 8253 timer registers. For now
we only emulate timer 0 which is the only timer that the BIOS code appears we only emulate timer 0 which is the only timer that the BIOS code appears
to use. to use.
****************************************************************************/ ****************************************************************************/
static void VGA_outpb( static void VGA_outpb (int port, u8 val)
int port,
u8 val)
{ {
switch (port) { switch (port) {
case 0x3C0: case 0x3C0:
/* 3C0 has funky characteristics because it can act as either /* 3C0 has funky characteristics because it can act as either
a data register or index register depending on the state a data register or index register depending on the state
of an internal flip flop in the hardware. Hence we have of an internal flip flop in the hardware. Hence we have
to emulate that functionality in here.*/ to emulate that functionality in here. */
if (_BE_env.flipFlop3C0 == 0) { if (_BE_env.flipFlop3C0 == 0) {
/* Access 3C0 as index register*/ /* Access 3C0 as index register */
_BE_env.emu3C0 = val; _BE_env.emu3C0 = val;
} } else {
else { /* Access 3C0 as data register */
/* Access 3C0 as data register*/
if (_BE_env.emu3C0 < ATT_C) if (_BE_env.emu3C0 < ATT_C)
_BE_env.emu3C1[_BE_env.emu3C0] = val; _BE_env.emu3C1[_BE_env.emu3C0] = val;
} }
@ -363,10 +358,12 @@ static void VGA_outpb(
_BE_env.emu3C6 = val; _BE_env.emu3C6 = val;
break; break;
case 0x3C7: case 0x3C7:
_BE_env.emu3C7 = (int)val * 3; _BE_env.emu3C7 = (int) val *3;
break; break;
case 0x3C8: case 0x3C8:
_BE_env.emu3C8 = (int)val * 3; _BE_env.emu3C8 = (int) val *3;
break; break;
case 0x3C9: case 0x3C9:
if (_BE_env.emu3C8 < PAL_C) if (_BE_env.emu3C8 < PAL_C)

1
drivers/bios_emulator/include/x86emu/prim_ops.h
View File

@ -139,4 +139,3 @@ u32 pop_long (void);
#endif #endif
#endif /* __X86EMU_PRIM_OPS_H */ #endif /* __X86EMU_PRIM_OPS_H */

4
drivers/bios_emulator/x86emu/decode.c
View File

@ -1121,7 +1121,6 @@ unsigned decode_rm10_address(
return 0; /* SHOULD NOT HAPPEN */ return 0; /* SHOULD NOT HAPPEN */
} }
/**************************************************************************** /****************************************************************************
PARAMETERS: PARAMETERS:
mod - modifier mod - modifier
@ -1143,6 +1142,3 @@ unsigned decode_rmXX_address(int mod, int rm)
return decode_rm01_address(rm); return decode_rm01_address(rm);
return decode_rm10_address(rm); return decode_rm10_address(rm);
} }

1
drivers/bios_emulator/x86emu/prim_ops.c
View File

@ -2443,4 +2443,3 @@ DB( if (CHECK_SP_ACCESS())
M.x86.R_SP += 4; M.x86.R_SP += 4;
return res; return res;
} }

84
include/radeon.h
View File

@ -90,7 +90,7 @@
#define MEM_IO_OE_CNTL 0x018C #define MEM_IO_OE_CNTL 0x018C
#define MC_CHIP_IO_OE_CNTL_AB 0x018C #define MC_CHIP_IO_OE_CNTL_AB 0x018C
#define MC_FB_LOCATION 0x0148 #define MC_FB_LOCATION 0x0148
//#define MC_FB_LOCATION 0x0188 /* #define MC_FB_LOCATION 0x0188 */
#define HOST_PATH_CNTL 0x0130 #define HOST_PATH_CNTL 0x0130
#define MEM_VGA_WP_SEL 0x0038 #define MEM_VGA_WP_SEL 0x0038
#define MEM_VGA_RP_SEL 0x003C #define MEM_VGA_RP_SEL 0x003C
@ -193,8 +193,8 @@
#define FP_V_SYNC_STRT_WID 0x02C8 #define FP_V_SYNC_STRT_WID 0x02C8
#define AUX_WINDOW_HORZ_CNTL 0x02D8 #define AUX_WINDOW_HORZ_CNTL 0x02D8
#define AUX_WINDOW_VERT_CNTL 0x02DC #define AUX_WINDOW_VERT_CNTL 0x02DC
//#define DDA_CONFIG 0x02e0 /* #define DDA_CONFIG 0x02e0 */
//#define DDA_ON_OFF 0x02e4 /* #define DDA_ON_OFF 0x02e4 */
#define DVI_I2C_CNTL_1 0x02e4 #define DVI_I2C_CNTL_1 0x02e4
#define GRPH_BUFFER_CNTL 0x02F0 #define GRPH_BUFFER_CNTL 0x02F0
#define GRPH2_BUFFER_CNTL 0x03F0 #define GRPH2_BUFFER_CNTL 0x03F0
@ -403,7 +403,7 @@
#define VGA_DDA_ON_OFF 0x02ec #define VGA_DDA_ON_OFF 0x02ec
#define TV_MASTER_CNTL 0x0800 #define TV_MASTER_CNTL 0x0800
//#define BASE_CODE 0x0f0b /* #define BASE_CODE 0x0f0b */
#define BIOS_0_SCRATCH 0x0010 #define BIOS_0_SCRATCH 0x0010
#define BIOS_1_SCRATCH 0x0014 #define BIOS_1_SCRATCH 0x0014
#define BIOS_2_SCRATCH 0x0018 #define BIOS_2_SCRATCH 0x0018
@ -572,7 +572,7 @@
/* FP bit constants */ /* FP bit constants */
#define FP_CRTC_H_TOTAL_MASK 0x000003ff #define FP_CRTC_H_TOTAL_MASK 000003ff
#define FP_CRTC_H_DISP_MASK 0x01ff0000 #define FP_CRTC_H_DISP_MASK 0x01ff0000
#define FP_CRTC_V_TOTAL_MASK 0x00000fff #define FP_CRTC_V_TOTAL_MASK 0x00000fff
#define FP_CRTC_V_DISP_MASK 0x0fff0000 #define FP_CRTC_V_DISP_MASK 0x0fff0000
@ -1000,7 +1000,7 @@
/* PAD_CTLR_STRENGTH */ /* PAD_CTLR_STRENGTH */
#define PAD_MANUAL_OVERRIDE 0x80000000 #define PAD_MANUAL_OVERRIDE 0x80000000
// pllCLK_PIN_CNTL /* pllCLK_PIN_CNTL */
#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
#define CLK_PIN_CNTL__OSC_EN 0x00000001L #define CLK_PIN_CNTL__OSC_EN 0x00000001L
#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
@ -1026,7 +1026,7 @@
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
// pllCLK_PWRMGT_CNTL /* pllCLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
@ -1051,7 +1051,7 @@
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
// pllP2PLL_CNTL /* pllP2PLL_CNTL */
#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
#define P2PLL_CNTL__P2PLL_RESET 0x00000001L #define P2PLL_CNTL__P2PLL_RESET 0x00000001L
#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
@ -1076,7 +1076,7 @@
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
// pllPIXCLKS_CNTL /* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
@ -1090,7 +1090,7 @@
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
// pllPIXCLKS_CNTL /* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
@ -1112,7 +1112,7 @@
#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
// pllP2PLL_DIV_0 /* pllP2PLL_DIV_0 */
#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
@ -1120,7 +1120,7 @@
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
// pllSCLK_CNTL /* pllSCLK_CNTL */
#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
@ -1160,7 +1160,7 @@
#define SCLK_CNTL__R300_FORCE_SU (1<<30) #define SCLK_CNTL__R300_FORCE_SU (1<<30)
#define SCLK_CNTL__FORCEON_MASK 0xffff8000L #define SCLK_CNTL__FORCEON_MASK 0xffff8000L
// pllSCLK_CNTL2 /* pllSCLK_CNTL2 */
#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
@ -1168,7 +1168,7 @@
#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) #define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
#define SCLK_CNTL2__R300_FORCE_GA (1<<15) #define SCLK_CNTL2__R300_FORCE_GA (1<<15)
// SCLK_MORE_CNTL /* SCLK_MORE_CNTL */
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
@ -1188,7 +1188,7 @@
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
#define SCLK_MORE_CNTL__FORCEON 0x00000700L #define SCLK_MORE_CNTL__FORCEON 0x00000700L
// MCLK_CNTL /* MCLK_CNTL */
#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
@ -1212,7 +1212,7 @@
#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
// MCLK_MISC /* MCLK_MISC */
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
@ -1242,7 +1242,7 @@
#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
// VCLK_ECP_CNTL /* VCLK_ECP_CNTL */
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
@ -1253,7 +1253,7 @@
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
// PLL_PWRMGT_CNTL /* PLL_PWRMGT_CNTL */
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
@ -1287,7 +1287,7 @@
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
// CLK_PWRMGT_CNTL /* CLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
@ -1332,7 +1332,7 @@
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
// BUS_CNTL1 /* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
@ -1356,7 +1356,7 @@
#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
#define BUS_CNTL1__AGPCLK_VALID 0x80000000L #define BUS_CNTL1__AGPCLK_VALID 0x80000000L
// BUS_CNTL1 /* BUS_CNTL1 */
#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
@ -1370,7 +1370,7 @@
#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
// CRTC_OFFSET_CNTL /* CRTC_OFFSET_CNTL */
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
@ -1395,7 +1395,7 @@
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
// CRTC_GEN_CNTL /* CRTC_GEN_CNTL */
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
@ -1416,7 +1416,7 @@
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
// CRTC2_GEN_CNTL /* CRTC2_GEN_CNTL */
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
@ -1448,7 +1448,7 @@
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
// AGP_CNTL /* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
@ -1488,7 +1488,7 @@
#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
// AGP_CNTL /* AGP_CNTL */
#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
@ -1511,7 +1511,7 @@
#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
// DISP_MISC_CNTL /* DISP_MISC_CNTL */
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
@ -1543,7 +1543,7 @@
#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
// DISP_PWR_MAN /* DISP_PWR_MAN */
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
@ -1572,15 +1572,15 @@
#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
// MC_IND_INDEX /* MC_IND_INDEX */
#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
// MC_IND_DATA /* MC_IND_DATA */
#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
// MC_CHP_IO_CNTL_A1 /* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
@ -1605,7 +1605,7 @@
#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
// MC_CHP_IO_CNTL_B1 /* MC_CHP_IO_CNTL_B1 */
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
@ -1630,7 +1630,7 @@
#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
// MC_CHP_IO_CNTL_A1 /* MC_CHP_IO_CNTL_A1 */
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
@ -1671,7 +1671,7 @@
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
// MC_CHP_IO_CNTL_B1 /* MC_CHP_IO_CNTL_B1 */
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
@ -1712,7 +1712,7 @@
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
// MEM_SDRAM_MODE_REG /* MEM_SDRAM_MODE_REG */
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
@ -1735,7 +1735,7 @@
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
// MEM_SDRAM_MODE_REG /* MEM_SDRAM_MODE_REG */
#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
@ -1749,7 +1749,7 @@
#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
// MEM_REFRESH_CNTL /* MEM_REFRESH_CNTL */
#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
@ -1779,7 +1779,7 @@
#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
// MC_STATUS /* MC_STATUS */
#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
@ -1797,7 +1797,7 @@
#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
// MDLL_CKO /* MDLL_CKO */
#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
#define MDLL_CKO__MCKOA_SLEEP 0x00000001L #define MDLL_CKO__MCKOA_SLEEP 0x00000001L
#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
@ -1821,7 +1821,7 @@
#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
// MDLL_RDCKA /* MDLL_RDCKA */
#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
@ -1849,7 +1849,7 @@
#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
// MDLL_RDCKB /* MDLL_RDCKB */
#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
@ -1981,6 +1981,4 @@
#define ixR300_MC_DLL_CNTL 0x002f #define ixR300_MC_DLL_CNTL 0x002f
#define NB_TOM 0x15C #define NB_TOM 0x15C
#endif /* _RADEON_H */ #endif /* _RADEON_H */