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powerpc/mpc85xx: Add clear_ddr_tlbs function

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This is useful when we just want to wipe out the TLBs.  There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function.  The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Becky Bruce 2011-07-18 18:49:15 -05:00 committed by Kumar Gala
parent ffadc441bc
commit 9cdfe28106
3 changed files with 33 additions and 11 deletions
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14
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -374,6 +374,8 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
unsigned int unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg); setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
static void dump_spd_ddr_reg(void) static void dump_spd_ddr_reg(void)
{ {
int i, j, k, m; int i, j, k, m;
@ -460,19 +462,9 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
unsigned long epn; unsigned long epn;
u32 tsize, valid, ptr; u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
int ddr_esel; int ddr_esel;
ptr = vstart; clear_ddr_tlbs_phys(p_addr, size>>20);
while (ptr < (vstart + size)) {
ddr_esel = find_tlb_idx((void *)ptr, 1);
if (ddr_esel != -1) {
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
disable_tlb(ddr_esel);
}
ptr += TSIZE_TO_BYTES(tsize);
}
/* Setup new tlb to cover the physical address */ /* Setup new tlb to cover the physical address */
setup_ddr_tlbs_phys(p_addr, size>>20); setup_ddr_tlbs_phys(p_addr, size>>20);

29
arch/powerpc/cpu/mpc85xx/tlb.c
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@ -300,4 +300,33 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
return return
setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
} }
/* Invalidate the DDR TLBs for the requested size */
void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
unsigned long epn;
u32 tsize, valid, ptr;
phys_addr_t rpn = 0;
int ddr_esel;
u64 memsize = (u64)memsize_in_meg << 20;
ptr = vstart;
while (ptr < (vstart + memsize)) {
ddr_esel = find_tlb_idx((void *)ptr, 1);
if (ddr_esel != -1) {
read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
disable_tlb(ddr_esel);
}
ptr += TSIZE_TO_BYTES(tsize);
}
}
void clear_ddr_tlbs(unsigned int memsize_in_meg)
{
clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}
#endif /* !CONFIG_NAND_SPL */ #endif /* !CONFIG_NAND_SPL */

1
arch/powerpc/include/asm/mmu.h
View File

@ -489,6 +489,7 @@ extern int find_free_tlbcam(void);
extern void print_tlbcam(void); extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);