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85xx: Add CPU 2 errata workaround to all 8548 boards

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All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Peter Tyser 2008-11-11 10:17:10 -06:00 committed by Andrew Fleming-AFLEMING
parent e57f0fa133
commit a2cd50ed6e
3 changed files with 13 additions and 19 deletions
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12
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -52,7 +52,6 @@ int checkboard (void)
uint pci_slot = get_pci_slot (); uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision (); uint cpu_board_rev = get_cpu_board_revision ();
uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot); get_board_version (), pci_slot);
@ -65,17 +64,6 @@ int checkboard (void)
*/ */
local_bus_init (); local_bus_init ();
svr = get_svr();
/*
* Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
* Fixed in Silicon Rev.2.1
*/
if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
ecm->eebpcr |= (1 << 16);
/* /*
* Hack TSEC 3 and 4 IO voltages. * Hack TSEC 3 and 4 IO voltages.
*/ */

7
board/sbc8548/sbc8548.c
View File

@ -61,13 +61,6 @@ int checkboard (void)
*/ */
local_bus_init (); local_bus_init ();
/*
* Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
*/
ecm->eebpcr |= (1 << 16);
/* /*
* Hack TSEC 3 and 4 IO voltages. * Hack TSEC 3 and 4 IO voltages.
*/ */

13
cpu/mpc85xx/cpu_init.c
View File

@ -174,6 +174,19 @@ void cpu_init_f (void)
{ {
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void); extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
/*
* CPU2 errata workaround: A core hang possible while executing
* a msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
* Fixed in silicon rev 2.1.
*/
if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
#endif
disable_tlb(14); disable_tlb(14);
disable_tlb(15); disable_tlb(15);