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net/designware: Consecutive writes must have delay

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This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
This commit is contained in:
Armando Visconti 2012-03-26 00:09:55 +00:00 committed by Joe Hershberger
parent 024333c96f
commit aa51005c3f
1 changed files with 1 additions and 2 deletions
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3
drivers/net/designware.c
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@ -175,8 +175,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
return 0; return 0;
} }