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85xx: Fix address map for 36-bit config of MPC8572DS

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When we introduced the 36-bit config of the MPC8572DS board we had the
wrong PCI MEM bus address map.  Additionally, the change to the address
map exposes a small issue in our dummy read on the ULI bus.  We need
to use the new mapping functions to handle that read properly in the
36-bit config.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-02-09 22:03:05 -06:00 committed by Andy Fleming
parent f8523cb081
commit ad97dce184
2 changed files with 10 additions and 5 deletions
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6
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -216,8 +216,10 @@ void pci_init_board(void)
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32); PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
debug(" uli1572 read to %x\n", temp32); void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
in_be32((unsigned *)temp32); temp32, 4, 0);
debug(" uli1572 read to %p\n", p);
in_be32(p);
} }
} else { } else {
printf (" PCIE3: disabled\n"); printf (" PCIE3: disabled\n");

9
include/configs/MPC8572DS.h
View File

@ -404,10 +404,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/* controller 3, direct to uli, tgtid 3, Base address 8000 */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#else #else
#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
#endif #endif
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
@ -422,10 +423,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else #else
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif #endif
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
@ -440,10 +442,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/* controller 1, Slot 1, tgtid 1, Base address a000 */ /* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#else #else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
#endif #endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */