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https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
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ppc: add support for ppc based board mgcoge2ne
The mgcoge2 board from keymile deploys two different processors. An ARM based Kirkwood for the "unit" part of the SW and a PPC for the "ne" part of the SW. Therefore in Linux and U-Boot the names for the board are mgcoge2un and mgcoge2ne. This patch adds the mgcoge2ne part of the board. The ppc part of mgboge2 is quite similar to mgcoge, therefore a generic header km82xx-common.h was introduced to collect all similiarities. Currently the only difference is that mgcoge2ne has a 64 MB numonyx NOR flash with a single die. The mgcoge has a dual die flash 2*32MB from spansion. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
effe5e8cda
commit
af895e4527
@ -428,6 +428,7 @@ Heiko Schocher <hs@denx.de>
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jupiter MPC5200
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jupiter MPC5200
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kmeter1 MPC8360
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kmeter1 MPC8360
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mgcoge MPC8247
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mgcoge MPC8247
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mgcoge2ne MPC8247
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mgcoge2un ARM926EJS (Kirkwood SoC)
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mgcoge2un ARM926EJS (Kirkwood SoC)
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mucmc52 MPC5200
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mucmc52 MPC5200
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muas3001 MPC8270
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muas3001 MPC8270
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@ -22,7 +22,7 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#if defined(CONFIG_MGCOGE)
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#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE)
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#include <mpc8260.h>
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#include <mpc8260.h>
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#endif
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#endif
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#include <ioports.h>
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#include <ioports.h>
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@ -343,7 +343,7 @@ int ivm_read_eeprom(void)
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#define DELAY_ABORT_SEQ 62
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#define DELAY_ABORT_SEQ 62
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#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
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#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
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#if defined(CONFIG_MGCOGE)
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#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGCOGE2NE)
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#define SDA_MASK 0x00010000
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#define SDA_MASK 0x00010000
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#define SCL_MASK 0x00020000
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#define SCL_MASK 0x00020000
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static void set_pin(int state, unsigned long mask)
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static void set_pin(int state, unsigned long mask)
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@ -284,7 +284,11 @@ phys_size_t initdram(int board_type)
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int checkboard(void)
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int checkboard(void)
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{
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{
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#if defined(CONFIG_MGCOGE)
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puts("Board: Keymile mgcoge");
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puts("Board: Keymile mgcoge");
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#else
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puts("Board: Keymile mgcoge2ne");
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#endif
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if (ethernet_present())
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if (ethernet_present())
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puts(" with PIGGY.");
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puts(" with PIGGY.");
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puts("\n");
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puts("\n");
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@ -440,6 +440,7 @@ PQ2FADS-ZU_66MHz_lowboot powerpc mpc8260 mpc8260ads freesca
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PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
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PQ2FADS-ZU_lowboot powerpc mpc8260 mpc8260ads freescale - MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000
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VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz
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VoVPN-GW_66MHz powerpc mpc8260 vovpn-gw funkwerk - VoVPN-GW:CLKIN_66MHz
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mgcoge powerpc mpc8260 - keymile
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mgcoge powerpc mpc8260 - keymile
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mgcoge2ne powerpc mpc8260 mgcoge keymile
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SCM powerpc mpc8260 - siemens
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SCM powerpc mpc8260 - siemens
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TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz
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TQM8255_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8255,300MHz
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TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz
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TQM8260_AA powerpc mpc8260 tqm8260 tqc - TQM8260:MPC8260,200MHz
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336
include/configs/km82xx-common.h
Normal file
336
include/configs/km82xx-common.h
Normal file
@ -0,0 +1,336 @@
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/*
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* (C) Copyright 2007-2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __KM82XX_COMMON
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#define __KM82XX_COMMON
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
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#undef CONFIG_CONS_NONE /* It's not on external UART */
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#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
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#define CONFIG_SYS_SMC_RXBUFLEN 128
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#define CONFIG_SYS_MAXIDLE 10
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/*
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* Select ethernet configuration
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*
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* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
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* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
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* SCC, 1-3 for FCC)
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*
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* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
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* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
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* must be unset.
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*/
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#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
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#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
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#undef CONFIG_ETHER_NONE /* No external Ethernet */
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#define CONFIG_NET_MULTI
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#define CONFIG_ETHER_INDEX 4
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#define CONFIG_HAS_ETH0
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#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
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#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
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#ifndef CONFIG_8260_CLKIN
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#define CONFIG_8260_CLKIN 66000000 /* in Hz */
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#endif
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#define BOOTFLASH_START 0xFE000000
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#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"app:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"3072k(free)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_DEF_ENV \
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"EEprom_ivm=pca9544a:70:4 \0" \
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"unlock=yes\0" \
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"newenv=" \
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"prot off 0xFE0C0000 +0x40000 && " \
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"era 0xFE0C0000 +0x40000\0" \
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"rootpath=/opt/eldk/ppc_82xx\0" \
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""
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (768 << 10)
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#define CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
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#define I2C_ACTIVE (iop->pdir |= 0x00010000)
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#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
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#define I2C_READ ((iop->pdat & 0x00010000) != 0)
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#define I2C_SDA(bit) do { \
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if (bit) \
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iop->pdat |= 0x00010000; \
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else \
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iop->pdat &= ~0x00010000; \
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} while (0)
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#define I2C_SCL(bit) do { \
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if (bit) \
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iop->pdat |= 0x00020000; \
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else \
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iop->pdat &= ~0x00020000; \
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} while (0)
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_IMMR 0xF0000000
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* Hard reset configuration word */
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#define CONFIG_SYS_HRCW_MASTER 0x0604b211
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/* No slaves */
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#define CONFIG_SYS_HRCW_SLAVE1 0
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#define CONFIG_SYS_HRCW_SLAVE2 0
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#define CONFIG_SYS_HRCW_SLAVE3 0
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#define CONFIG_SYS_HRCW_SLAVE4 0
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#define CONFIG_SYS_HRCW_SLAVE5 0
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#define CONFIG_SYS_HRCW_SLAVE6 0
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#define CONFIG_SYS_HRCW_SLAVE7 0
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#define CONFIG_SYS_HID0_INIT 0
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#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
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#define CONFIG_SYS_HID2 0
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#define CONFIG_SYS_SIUMCR 0x4020c200
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#define CONFIG_SYS_SYPCR 0xFFFFFFC3
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#define CONFIG_SYS_BCR 0x10000000
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#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
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/*
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*-----------------------------------------------------------------------
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* RMR - Reset Mode Register 5-5
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*-----------------------------------------------------------------------
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* turn on Checkstop Reset Enable
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*/
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#define CONFIG_SYS_RMR 0
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/*
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*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
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/*
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*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*
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*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RCCR 0
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/*
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* Init Memory Controller:
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*
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* Bank Bus Machine PortSz Device
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* ---- --- ------- ------ ------
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* 0 60x GPCM 8 bit FLASH
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* 1 60x SDRAM 32 bit SDRAM
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* 3 60x GPCM 8 bit GPIO/PIGGY
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* 5 60x GPCM 16 bit CFG-Flash
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*
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*/
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/* Bank 0 - FLASH
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*/
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
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BRx_PS_8 |\
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BRx_MS_GPCM_P |\
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BRx_V)
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#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
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ORxG_CSNT |\
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ORxG_ACS_DIV2 |\
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ORxG_SCY_5_CLK |\
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ORxG_TRLX)
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/*
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* Bank 1 - 60x bus SDRAM
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*/
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#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
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#define CONFIG_SYS_MPTPR 0x1800
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/*
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*-----------------------------------------------------------------------------
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* Address for Mode Register Set (MRS) command
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*-----------------------------------------------------------------------------
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*/
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#define CONFIG_SYS_MRS_OFFS 0x00000110
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#define CONFIG_SYS_PSRT 0x0e
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
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BRx_PS_64 |\
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BRx_MS_SDRAM_P |\
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BRx_V)
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#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
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/*
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* SDRAM initialization values
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*/
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#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
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ORxS_BPD_8 |\
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ORxS_ROWST_PBI0_A7 |\
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ORxS_NUMR_13)
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||||||
|
#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
|
||||||
|
PSDMR_BSMA_A14_A16 |\
|
||||||
|
PSDMR_SDA10_PBI0_A9 |\
|
||||||
|
PSDMR_RFRC_5_CLK |\
|
||||||
|
PSDMR_PRETOACT_2W |\
|
||||||
|
PSDMR_ACTTORW_2W |\
|
||||||
|
PSDMR_LDOTOPRE_1C |\
|
||||||
|
PSDMR_WRC_1C |\
|
||||||
|
PSDMR_CL_2)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO/PIGGY on CS3 initialization values
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_PIGGY_BASE 0x30000000
|
||||||
|
#define CONFIG_SYS_PIGGY_SIZE 128
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
|
||||||
|
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
|
||||||
|
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||||
|
ORxG_SCY_3_CLK | ORxG_TRLX)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board FPGA on CS4 initialization values
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_FPGA_BASE 0x40000000
|
||||||
|
#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
|
||||||
|
|
||||||
|
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
|
||||||
|
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
|
||||||
|
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||||
|
ORxG_SCY_3_CLK | ORxG_TRLX)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CFG-Flash on CS5 initialization values
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
|
||||||
|
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
|
||||||
|
CONFIG_SYS_FLASH_SIZE_2) |\
|
||||||
|
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||||
|
ORxG_SCY_5_CLK | ORxG_TRLX)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
||||||
|
|
||||||
|
/* pass open firmware flat tree */
|
||||||
|
#define CONFIG_FIT 1
|
||||||
|
#define CONFIG_OF_LIBFDT 1
|
||||||
|
#define CONFIG_OF_BOARD_SETUP 1
|
||||||
|
|
||||||
|
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||||
|
#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
|
||||||
|
|
||||||
|
#endif /* __KM82XX_COMMON */
|
||||||
@ -39,72 +39,6 @@
|
|||||||
#include "keymile-common.h"
|
#include "keymile-common.h"
|
||||||
#include "km-powerpc.h"
|
#include "km-powerpc.h"
|
||||||
|
|
||||||
/*
|
|
||||||
* Select serial console configuration
|
|
||||||
*
|
|
||||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
|
||||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
|
||||||
* for SCC).
|
|
||||||
*/
|
|
||||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
|
|
||||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
|
||||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
|
||||||
#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
|
|
||||||
#define CONFIG_SYS_SMC_RXBUFLEN 128
|
|
||||||
#define CONFIG_SYS_MAXIDLE 10
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Select ethernet configuration
|
|
||||||
*
|
|
||||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
|
|
||||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
|
|
||||||
* SCC, 1-3 for FCC)
|
|
||||||
*
|
|
||||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
|
|
||||||
* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
|
|
||||||
* must be unset.
|
|
||||||
*/
|
|
||||||
#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
|
|
||||||
#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
|
|
||||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
|
||||||
#define CONFIG_NET_MULTI
|
|
||||||
|
|
||||||
#define CONFIG_ETHER_INDEX 4
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
|
|
||||||
|
|
||||||
# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
|
|
||||||
|
|
||||||
#ifndef CONFIG_8260_CLKIN
|
|
||||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define BOOTFLASH_START 0xFE000000
|
|
||||||
|
|
||||||
#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
|
|
||||||
|
|
||||||
#define MTDIDS_DEFAULT "nor3=app"
|
|
||||||
#define MTDPARTS_DEFAULT "mtdparts=" \
|
|
||||||
"app:" \
|
|
||||||
"768k(u-boot)," \
|
|
||||||
"128k(env)," \
|
|
||||||
"128k(envred)," \
|
|
||||||
"3072k(free)," \
|
|
||||||
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Default environment settings
|
|
||||||
*/
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
CONFIG_KM_DEF_ENV \
|
|
||||||
"EEprom_ivm=pca9544a:70:4 \0" \
|
|
||||||
"unlock=yes\0" \
|
|
||||||
"newenv=" \
|
|
||||||
"prot off 0xFE0C0000 +0x40000 && " \
|
|
||||||
"era 0xFE0C0000 +0x40000\0" \
|
|
||||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
|
||||||
""
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||||
#define CONFIG_SYS_FLASH_SIZE 32
|
#define CONFIG_SYS_FLASH_SIZE 32
|
||||||
@ -122,250 +56,10 @@
|
|||||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
|
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
|
||||||
CONFIG_SYS_FLASH_BASE_1, \
|
CONFIG_SYS_FLASH_BASE_1, \
|
||||||
CONFIG_SYS_FLASH_BASE_2 }
|
CONFIG_SYS_FLASH_BASE_2 }
|
||||||
|
#define MTDIDS_DEFAULT "nor3=app"
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
/* include further common stuff for all keymile 82xx boards */
|
||||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
#include "km82xx-common.h"
|
||||||
#define CONFIG_SYS_RAMBOOT
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (768 << 10)
|
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH
|
|
||||||
|
|
||||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
|
||||||
CONFIG_SYS_MONITOR_LEN)
|
|
||||||
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
|
|
||||||
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
|
||||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
|
||||||
CONFIG_ENV_SECT_SIZE)
|
|
||||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
|
||||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
|
||||||
#define CONFIG_ENV_BUFFER_PRINT
|
|
||||||
|
|
||||||
/* enable I2C and select the hardware/software driver */
|
|
||||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
|
||||||
#define CONFIG_SOFT_I2C /* I2C bit-banged */
|
|
||||||
#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
|
|
||||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Software (bit-bang) I2C driver configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
|
||||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
|
||||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
|
||||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
|
||||||
#define I2C_SDA(bit) do { \
|
|
||||||
if (bit) \
|
|
||||||
iop->pdat |= 0x00010000; \
|
|
||||||
else \
|
|
||||||
iop->pdat &= ~0x00010000; \
|
|
||||||
} while (0)
|
|
||||||
#define I2C_SCL(bit) do { \
|
|
||||||
if (bit) \
|
|
||||||
iop->pdat |= 0x00020000; \
|
|
||||||
else \
|
|
||||||
iop->pdat &= ~0x00020000; \
|
|
||||||
} while (0)
|
|
||||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
|
||||||
|
|
||||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
|
||||||
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
|
||||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
|
||||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
|
||||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
|
||||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
|
||||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_IMMR 0xF0000000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
|
||||||
GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
/* Hard reset configuration word */
|
|
||||||
#define CONFIG_SYS_HRCW_MASTER 0x0604b211
|
|
||||||
|
|
||||||
/* No slaves */
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
|
||||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HID0_INIT 0
|
|
||||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HID2 0
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SIUMCR 0x4020c200
|
|
||||||
#define CONFIG_SYS_SYPCR 0xFFFFFFC3
|
|
||||||
#define CONFIG_SYS_BCR 0x10000000
|
|
||||||
#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* RMR - Reset Mode Register 5-5
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* turn on Checkstop Reset Enable
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_RMR 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* TMCNTSC - Time Counter Status and Control 4-40
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
|
||||||
* and enable Time Counter
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
|
||||||
* Periodic timer
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* RCCR - RISC Controller Configuration 13-7
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_RCCR 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller:
|
|
||||||
*
|
|
||||||
* Bank Bus Machine PortSz Device
|
|
||||||
* ---- --- ------- ------ ------
|
|
||||||
* 0 60x GPCM 8 bit FLASH
|
|
||||||
* 1 60x SDRAM 32 bit SDRAM
|
|
||||||
* 3 60x GPCM 8 bit GPIO/PIGGY
|
|
||||||
* 5 60x GPCM 16 bit CFG-Flash
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/* Bank 0 - FLASH
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
|
|
||||||
BRx_PS_8 |\
|
|
||||||
BRx_MS_GPCM_P |\
|
|
||||||
BRx_V)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
|
|
||||||
ORxG_CSNT |\
|
|
||||||
ORxG_ACS_DIV2 |\
|
|
||||||
ORxG_SCY_5_CLK |\
|
|
||||||
ORxG_TRLX )
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Bank 1 - 60x bus SDRAM
|
|
||||||
*/
|
|
||||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
|
|
||||||
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MPTPR 0x1800
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
* Address for Mode Register Set (MRS) command
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_MRS_OFFS 0x00000110
|
|
||||||
#define CONFIG_SYS_PSRT 0x0e
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
|
|
||||||
BRx_PS_64 |\
|
|
||||||
BRx_MS_SDRAM_P |\
|
|
||||||
BRx_V)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM initialization values
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
|
||||||
ORxS_BPD_8 |\
|
|
||||||
ORxS_ROWST_PBI0_A7 |\
|
|
||||||
ORxS_NUMR_13)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
|
|
||||||
PSDMR_BSMA_A14_A16 |\
|
|
||||||
PSDMR_SDA10_PBI0_A9 |\
|
|
||||||
PSDMR_RFRC_5_CLK |\
|
|
||||||
PSDMR_PRETOACT_2W |\
|
|
||||||
PSDMR_ACTTORW_2W |\
|
|
||||||
PSDMR_LDOTOPRE_1C |\
|
|
||||||
PSDMR_WRC_1C |\
|
|
||||||
PSDMR_CL_2)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* GPIO/PIGGY on CS3 initialization values
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PIGGY_BASE 0x30000000
|
|
||||||
#define CONFIG_SYS_PIGGY_SIZE 128
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
|
|
||||||
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
|
|
||||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
|
||||||
ORxG_SCY_3_CLK | ORxG_TRLX )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Board FPGA on CS4 initialization values
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FPGA_BASE 0x40000000
|
|
||||||
#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
|
|
||||||
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
|
|
||||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
|
||||||
ORxG_SCY_3_CLK | ORxG_TRLX )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* CFG-Flash on CS5 initialization values
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
|
|
||||||
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
|
|
||||||
CONFIG_SYS_FLASH_SIZE_2) |\
|
|
||||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
|
||||||
ORxG_SCY_5_CLK | ORxG_TRLX )
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
|
||||||
|
|
||||||
/* pass open firmware flat tree */
|
|
||||||
#define CONFIG_FIT
|
|
||||||
#define CONFIG_OF_LIBFDT
|
|
||||||
#define CONFIG_OF_BOARD_SETUP
|
|
||||||
|
|
||||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
|
||||||
#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
|
|
||||||
|
|
||||||
/* enable last_stage_init */
|
/* enable last_stage_init */
|
||||||
#define CONFIG_LAST_STAGE_INIT 1
|
#define CONFIG_LAST_STAGE_INIT 1
|
||||||
|
|||||||
64
include/configs/mgcoge2ne.h
Normal file
64
include/configs/mgcoge2ne.h
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2007-2010
|
||||||
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MGCOGE2NE
|
||||||
|
#define __MGCOGE2NE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options
|
||||||
|
* (easy to change)
|
||||||
|
*/
|
||||||
|
#define CONFIG_MPC8247
|
||||||
|
#define CONFIG_MGCOGE
|
||||||
|
#define CONFIG_HOSTNAME mgcoge2ne
|
||||||
|
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||||
|
|
||||||
|
/* include common defines/options for all Keymile boards */
|
||||||
|
#include "keymile-common.h"
|
||||||
|
#include "km-powerpc.h"
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||||
|
#define CONFIG_SYS_FLASH_BASE 0xFE000000
|
||||||
|
#define CONFIG_SYS_FLASH_SIZE 32
|
||||||
|
#define CONFIG_SYS_FLASH_CFI
|
||||||
|
#define CONFIG_FLASH_CFI_DRIVER
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
|
||||||
|
#define CONFIG_SYS_MAX_FLASH_SECT 512 /*
|
||||||
|
* max num of sects on one
|
||||||
|
* chip
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_BASE_1 0x50000000
|
||||||
|
#define CONFIG_SYS_FLASH_SIZE_1 64
|
||||||
|
#define CONFIG_SYS_FLASH_SIZE_2 0
|
||||||
|
|
||||||
|
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
|
||||||
|
CONFIG_SYS_FLASH_BASE_1 }
|
||||||
|
|
||||||
|
#define MTDIDS_DEFAULT "nor2=app"
|
||||||
|
|
||||||
|
/* include further common stuff for all keymile 82xx boards */
|
||||||
|
#include "km82xx-common.h"
|
||||||
|
|
||||||
|
#endif /* __MGCOGE2NE */
|
||||||
Loading…
x
Reference in New Issue
Block a user