From 9c84709eedce9c680dd695984ab7d2328f4f04f5 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 1 Nov 2007 12:23:29 -0500 Subject: [PATCH 1/3] 86xx: Fix broken variable reference when #def DEBUGing. Sometimes you can't reference the DDR2 controller variables. Signed-off-by: Jon Loeliger --- cpu/mpc86xx/spd_sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 059097f51..d57bcdf2c 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1270,10 +1270,12 @@ spd_sdram(void) debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); } + + debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); + #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ - debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", - memsize_ddr1, memsize_ddr2); + debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1); /* * If neither DDR controller is enabled return 0. From a8318ec205c8e8794b5f9f1b8584abadb440e8ba Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 26 Oct 2007 18:32:00 +0800 Subject: [PATCH 2/3] make 8610 board use pixis reset Signed-off-by: Jason Jin --- cpu/mpc86xx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index bbc0cd600..11354d38d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -131,7 +131,7 @@ checkcpu(void) static inline void soft_restart(unsigned long addr) { -#ifndef CONFIG_MPC8641HPCN +#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) /* * SRR0 has system reset vector, SRR1 has default MSR value @@ -159,7 +159,7 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#ifndef CONFIG_MPC8641HPCN +#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) #ifdef CFG_RESET_ADDRESS ulong addr = CFG_RESET_ADDRESS; From 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Mon, 29 Oct 2007 19:26:21 +0800 Subject: [PATCH 3/3] Unify pixis_reset altbank across board families Basically, refactor the CFG_PIXIS_VBOOT_MASK values into the separate board config files. Signed-off-by: Jason Jin Signed-off-by: Jon Loeliger --- board/freescale/common/pixis.c | 5 ++++- include/configs/MPC8544DS.h | 1 + include/configs/MPC8641HPCN.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index fd99a938c..45dcf4dab 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set) out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); } +#ifndef CFG_PIXIS_VBOOT_MASK +#define CFG_PIXIS_VBOOT_MASK 0x40 +#endif void set_altbank(void) { u8 tmp; tmp = in8(PIXIS_BASE + PIXIS_VBOOT); - tmp ^= 0x40; + tmp ^= CFG_PIXIS_VBOOT_MASK; out8(PIXIS_BASE + PIXIS_VBOOT, tmp); } diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index f580ccade..13e2a2c07 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ /* define to use L1 as initial stack */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index aa6dbc47a..6f8724026 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */