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Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8

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This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.

Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Robert Delien 2012-02-26 12:15:05 +00:00 committed by Albert ARIBAUD
parent 40083c52f7
commit b228e14e96
19 changed files with 441 additions and 437 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/cpu/arm926ejs/mx28/clock.c
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@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
return; return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
(ssp * sizeof(struct mx28_register)); (ssp * sizeof(struct mx28_register_32));
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE); clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
while (readl(clkreg) & CLKCTRL_SSP_CLKGATE) while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
return XTAL_FREQ_KHZ; return XTAL_FREQ_KHZ;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
(ssp * sizeof(struct mx28_register)); (ssp * sizeof(struct mx28_register_32));
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK; tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;

6
arch/arm/cpu/arm926ejs/mx28/iomux.c
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@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
{ {
u32 reg, ofs, bp, bm; u32 reg, ofs, bp, bm;
void *iomux_base = (void *)MXS_PINCTRL_BASE; void *iomux_base = (void *)MXS_PINCTRL_BASE;
struct mx28_register *mxs_reg; struct mx28_register_32 *mxs_reg;
/* muxsel */ /* muxsel */
ofs = 0x100; ofs = 0x100;
@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
/* vol */ /* vol */
if (PAD_VOL_VALID(pad)) { if (PAD_VOL_VALID(pad)) {
bp = PAD_PIN(pad) % 8 * 4 + 2; bp = PAD_PIN(pad) % 8 * 4 + 2;
mxs_reg = (struct mx28_register *)(iomux_base + ofs); mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
if (PAD_VOL(pad)) if (PAD_VOL(pad))
writel(1 << bp, &mxs_reg->reg_set); writel(1 << bp, &mxs_reg->reg_set);
else else
@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
ofs = PULL_OFFSET; ofs = PULL_OFFSET;
ofs += PAD_BANK(pad) * 0x10; ofs += PAD_BANK(pad) * 0x10;
bp = PAD_PIN(pad); bp = PAD_PIN(pad);
mxs_reg = (struct mx28_register *)(iomux_base + ofs); mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
if (PAD_PULL(pad)) if (PAD_PULL(pad))
writel(1 << bp, &mxs_reg->reg_set); writel(1 << bp, &mxs_reg->reg_set);
else else

6
arch/arm/cpu/arm926ejs/mx28/mx28.c
View File

@ -63,7 +63,7 @@ void reset_cpu(ulong ignored)
; ;
} }
int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout) int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
{ {
while (--timeout) { while (--timeout) {
if ((readl(&reg->reg) & mask) == mask) if ((readl(&reg->reg) & mask) == mask)
@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
return !timeout; return !timeout;
} }
int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout) int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
{ {
while (--timeout) { while (--timeout) {
if ((readl(&reg->reg) & mask) == 0) if ((readl(&reg->reg) & mask) == 0)
@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
return !timeout; return !timeout;
} }
int mx28_reset_block(struct mx28_register *reg) int mx28_reset_block(struct mx28_register_32 *reg)
{ {
/* Clear SFTRST */ /* Clear SFTRST */
writel(MX28_BLOCK_SFTRST, &reg->reg_clr); writel(MX28_BLOCK_SFTRST, &reg->reg_clr);

254
arch/arm/include/asm/arch-mx28/regs-apbh.h
View File

@ -30,142 +30,142 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_apbh_regs { struct mx28_apbh_regs {
mx28_reg(hw_apbh_ctrl0) mx28_reg_32(hw_apbh_ctrl0)
mx28_reg(hw_apbh_ctrl1) mx28_reg_32(hw_apbh_ctrl1)
mx28_reg(hw_apbh_ctrl2) mx28_reg_32(hw_apbh_ctrl2)
mx28_reg(hw_apbh_channel_ctrl) mx28_reg_32(hw_apbh_channel_ctrl)
mx28_reg(hw_apbh_devsel) mx28_reg_32(hw_apbh_devsel)
mx28_reg(hw_apbh_dma_burst_size) mx28_reg_32(hw_apbh_dma_burst_size)
mx28_reg(hw_apbh_debug) mx28_reg_32(hw_apbh_debug)
uint32_t reserved[36]; uint32_t reserved[36];
union { union {
struct { struct {
mx28_reg(hw_apbh_ch_curcmdar) mx28_reg_32(hw_apbh_ch_curcmdar)
mx28_reg(hw_apbh_ch_nxtcmdar) mx28_reg_32(hw_apbh_ch_nxtcmdar)
mx28_reg(hw_apbh_ch_cmd) mx28_reg_32(hw_apbh_ch_cmd)
mx28_reg(hw_apbh_ch_bar) mx28_reg_32(hw_apbh_ch_bar)
mx28_reg(hw_apbh_ch_sema) mx28_reg_32(hw_apbh_ch_sema)
mx28_reg(hw_apbh_ch_debug1) mx28_reg_32(hw_apbh_ch_debug1)
mx28_reg(hw_apbh_ch_debug2) mx28_reg_32(hw_apbh_ch_debug2)
} ch[16]; } ch[16];
struct { struct {
mx28_reg(hw_apbh_ch0_curcmdar) mx28_reg_32(hw_apbh_ch0_curcmdar)
mx28_reg(hw_apbh_ch0_nxtcmdar) mx28_reg_32(hw_apbh_ch0_nxtcmdar)
mx28_reg(hw_apbh_ch0_cmd) mx28_reg_32(hw_apbh_ch0_cmd)
mx28_reg(hw_apbh_ch0_bar) mx28_reg_32(hw_apbh_ch0_bar)
mx28_reg(hw_apbh_ch0_sema) mx28_reg_32(hw_apbh_ch0_sema)
mx28_reg(hw_apbh_ch0_debug1) mx28_reg_32(hw_apbh_ch0_debug1)
mx28_reg(hw_apbh_ch0_debug2) mx28_reg_32(hw_apbh_ch0_debug2)
mx28_reg(hw_apbh_ch1_curcmdar) mx28_reg_32(hw_apbh_ch1_curcmdar)
mx28_reg(hw_apbh_ch1_nxtcmdar) mx28_reg_32(hw_apbh_ch1_nxtcmdar)
mx28_reg(hw_apbh_ch1_cmd) mx28_reg_32(hw_apbh_ch1_cmd)
mx28_reg(hw_apbh_ch1_bar) mx28_reg_32(hw_apbh_ch1_bar)
mx28_reg(hw_apbh_ch1_sema) mx28_reg_32(hw_apbh_ch1_sema)
mx28_reg(hw_apbh_ch1_debug1) mx28_reg_32(hw_apbh_ch1_debug1)
mx28_reg(hw_apbh_ch1_debug2) mx28_reg_32(hw_apbh_ch1_debug2)
mx28_reg(hw_apbh_ch2_curcmdar) mx28_reg_32(hw_apbh_ch2_curcmdar)
mx28_reg(hw_apbh_ch2_nxtcmdar) mx28_reg_32(hw_apbh_ch2_nxtcmdar)
mx28_reg(hw_apbh_ch2_cmd) mx28_reg_32(hw_apbh_ch2_cmd)
mx28_reg(hw_apbh_ch2_bar) mx28_reg_32(hw_apbh_ch2_bar)
mx28_reg(hw_apbh_ch2_sema) mx28_reg_32(hw_apbh_ch2_sema)
mx28_reg(hw_apbh_ch2_debug1) mx28_reg_32(hw_apbh_ch2_debug1)
mx28_reg(hw_apbh_ch2_debug2) mx28_reg_32(hw_apbh_ch2_debug2)
mx28_reg(hw_apbh_ch3_curcmdar) mx28_reg_32(hw_apbh_ch3_curcmdar)
mx28_reg(hw_apbh_ch3_nxtcmdar) mx28_reg_32(hw_apbh_ch3_nxtcmdar)
mx28_reg(hw_apbh_ch3_cmd) mx28_reg_32(hw_apbh_ch3_cmd)
mx28_reg(hw_apbh_ch3_bar) mx28_reg_32(hw_apbh_ch3_bar)
mx28_reg(hw_apbh_ch3_sema) mx28_reg_32(hw_apbh_ch3_sema)
mx28_reg(hw_apbh_ch3_debug1) mx28_reg_32(hw_apbh_ch3_debug1)
mx28_reg(hw_apbh_ch3_debug2) mx28_reg_32(hw_apbh_ch3_debug2)
mx28_reg(hw_apbh_ch4_curcmdar) mx28_reg_32(hw_apbh_ch4_curcmdar)
mx28_reg(hw_apbh_ch4_nxtcmdar) mx28_reg_32(hw_apbh_ch4_nxtcmdar)
mx28_reg(hw_apbh_ch4_cmd) mx28_reg_32(hw_apbh_ch4_cmd)
mx28_reg(hw_apbh_ch4_bar) mx28_reg_32(hw_apbh_ch4_bar)
mx28_reg(hw_apbh_ch4_sema) mx28_reg_32(hw_apbh_ch4_sema)
mx28_reg(hw_apbh_ch4_debug1) mx28_reg_32(hw_apbh_ch4_debug1)
mx28_reg(hw_apbh_ch4_debug2) mx28_reg_32(hw_apbh_ch4_debug2)
mx28_reg(hw_apbh_ch5_curcmdar) mx28_reg_32(hw_apbh_ch5_curcmdar)
mx28_reg(hw_apbh_ch5_nxtcmdar) mx28_reg_32(hw_apbh_ch5_nxtcmdar)
mx28_reg(hw_apbh_ch5_cmd) mx28_reg_32(hw_apbh_ch5_cmd)
mx28_reg(hw_apbh_ch5_bar) mx28_reg_32(hw_apbh_ch5_bar)
mx28_reg(hw_apbh_ch5_sema) mx28_reg_32(hw_apbh_ch5_sema)
mx28_reg(hw_apbh_ch5_debug1) mx28_reg_32(hw_apbh_ch5_debug1)
mx28_reg(hw_apbh_ch5_debug2) mx28_reg_32(hw_apbh_ch5_debug2)
mx28_reg(hw_apbh_ch6_curcmdar) mx28_reg_32(hw_apbh_ch6_curcmdar)
mx28_reg(hw_apbh_ch6_nxtcmdar) mx28_reg_32(hw_apbh_ch6_nxtcmdar)
mx28_reg(hw_apbh_ch6_cmd) mx28_reg_32(hw_apbh_ch6_cmd)
mx28_reg(hw_apbh_ch6_bar) mx28_reg_32(hw_apbh_ch6_bar)
mx28_reg(hw_apbh_ch6_sema) mx28_reg_32(hw_apbh_ch6_sema)
mx28_reg(hw_apbh_ch6_debug1) mx28_reg_32(hw_apbh_ch6_debug1)
mx28_reg(hw_apbh_ch6_debug2) mx28_reg_32(hw_apbh_ch6_debug2)
mx28_reg(hw_apbh_ch7_curcmdar) mx28_reg_32(hw_apbh_ch7_curcmdar)
mx28_reg(hw_apbh_ch7_nxtcmdar) mx28_reg_32(hw_apbh_ch7_nxtcmdar)
mx28_reg(hw_apbh_ch7_cmd) mx28_reg_32(hw_apbh_ch7_cmd)
mx28_reg(hw_apbh_ch7_bar) mx28_reg_32(hw_apbh_ch7_bar)
mx28_reg(hw_apbh_ch7_sema) mx28_reg_32(hw_apbh_ch7_sema)
mx28_reg(hw_apbh_ch7_debug1) mx28_reg_32(hw_apbh_ch7_debug1)
mx28_reg(hw_apbh_ch7_debug2) mx28_reg_32(hw_apbh_ch7_debug2)
mx28_reg(hw_apbh_ch8_curcmdar) mx28_reg_32(hw_apbh_ch8_curcmdar)
mx28_reg(hw_apbh_ch8_nxtcmdar) mx28_reg_32(hw_apbh_ch8_nxtcmdar)
mx28_reg(hw_apbh_ch8_cmd) mx28_reg_32(hw_apbh_ch8_cmd)
mx28_reg(hw_apbh_ch8_bar) mx28_reg_32(hw_apbh_ch8_bar)
mx28_reg(hw_apbh_ch8_sema) mx28_reg_32(hw_apbh_ch8_sema)
mx28_reg(hw_apbh_ch8_debug1) mx28_reg_32(hw_apbh_ch8_debug1)
mx28_reg(hw_apbh_ch8_debug2) mx28_reg_32(hw_apbh_ch8_debug2)
mx28_reg(hw_apbh_ch9_curcmdar) mx28_reg_32(hw_apbh_ch9_curcmdar)
mx28_reg(hw_apbh_ch9_nxtcmdar) mx28_reg_32(hw_apbh_ch9_nxtcmdar)
mx28_reg(hw_apbh_ch9_cmd) mx28_reg_32(hw_apbh_ch9_cmd)
mx28_reg(hw_apbh_ch9_bar) mx28_reg_32(hw_apbh_ch9_bar)
mx28_reg(hw_apbh_ch9_sema) mx28_reg_32(hw_apbh_ch9_sema)
mx28_reg(hw_apbh_ch9_debug1) mx28_reg_32(hw_apbh_ch9_debug1)
mx28_reg(hw_apbh_ch9_debug2) mx28_reg_32(hw_apbh_ch9_debug2)
mx28_reg(hw_apbh_ch10_curcmdar) mx28_reg_32(hw_apbh_ch10_curcmdar)
mx28_reg(hw_apbh_ch10_nxtcmdar) mx28_reg_32(hw_apbh_ch10_nxtcmdar)
mx28_reg(hw_apbh_ch10_cmd) mx28_reg_32(hw_apbh_ch10_cmd)
mx28_reg(hw_apbh_ch10_bar) mx28_reg_32(hw_apbh_ch10_bar)
mx28_reg(hw_apbh_ch10_sema) mx28_reg_32(hw_apbh_ch10_sema)
mx28_reg(hw_apbh_ch10_debug1) mx28_reg_32(hw_apbh_ch10_debug1)
mx28_reg(hw_apbh_ch10_debug2) mx28_reg_32(hw_apbh_ch10_debug2)
mx28_reg(hw_apbh_ch11_curcmdar) mx28_reg_32(hw_apbh_ch11_curcmdar)
mx28_reg(hw_apbh_ch11_nxtcmdar) mx28_reg_32(hw_apbh_ch11_nxtcmdar)
mx28_reg(hw_apbh_ch11_cmd) mx28_reg_32(hw_apbh_ch11_cmd)
mx28_reg(hw_apbh_ch11_bar) mx28_reg_32(hw_apbh_ch11_bar)
mx28_reg(hw_apbh_ch11_sema) mx28_reg_32(hw_apbh_ch11_sema)
mx28_reg(hw_apbh_ch11_debug1) mx28_reg_32(hw_apbh_ch11_debug1)
mx28_reg(hw_apbh_ch11_debug2) mx28_reg_32(hw_apbh_ch11_debug2)
mx28_reg(hw_apbh_ch12_curcmdar) mx28_reg_32(hw_apbh_ch12_curcmdar)
mx28_reg(hw_apbh_ch12_nxtcmdar) mx28_reg_32(hw_apbh_ch12_nxtcmdar)
mx28_reg(hw_apbh_ch12_cmd) mx28_reg_32(hw_apbh_ch12_cmd)
mx28_reg(hw_apbh_ch12_bar) mx28_reg_32(hw_apbh_ch12_bar)
mx28_reg(hw_apbh_ch12_sema) mx28_reg_32(hw_apbh_ch12_sema)
mx28_reg(hw_apbh_ch12_debug1) mx28_reg_32(hw_apbh_ch12_debug1)
mx28_reg(hw_apbh_ch12_debug2) mx28_reg_32(hw_apbh_ch12_debug2)
mx28_reg(hw_apbh_ch13_curcmdar) mx28_reg_32(hw_apbh_ch13_curcmdar)
mx28_reg(hw_apbh_ch13_nxtcmdar) mx28_reg_32(hw_apbh_ch13_nxtcmdar)
mx28_reg(hw_apbh_ch13_cmd) mx28_reg_32(hw_apbh_ch13_cmd)
mx28_reg(hw_apbh_ch13_bar) mx28_reg_32(hw_apbh_ch13_bar)
mx28_reg(hw_apbh_ch13_sema) mx28_reg_32(hw_apbh_ch13_sema)
mx28_reg(hw_apbh_ch13_debug1) mx28_reg_32(hw_apbh_ch13_debug1)
mx28_reg(hw_apbh_ch13_debug2) mx28_reg_32(hw_apbh_ch13_debug2)
mx28_reg(hw_apbh_ch14_curcmdar) mx28_reg_32(hw_apbh_ch14_curcmdar)
mx28_reg(hw_apbh_ch14_nxtcmdar) mx28_reg_32(hw_apbh_ch14_nxtcmdar)
mx28_reg(hw_apbh_ch14_cmd) mx28_reg_32(hw_apbh_ch14_cmd)
mx28_reg(hw_apbh_ch14_bar) mx28_reg_32(hw_apbh_ch14_bar)
mx28_reg(hw_apbh_ch14_sema) mx28_reg_32(hw_apbh_ch14_sema)
mx28_reg(hw_apbh_ch14_debug1) mx28_reg_32(hw_apbh_ch14_debug1)
mx28_reg(hw_apbh_ch14_debug2) mx28_reg_32(hw_apbh_ch14_debug2)
mx28_reg(hw_apbh_ch15_curcmdar) mx28_reg_32(hw_apbh_ch15_curcmdar)
mx28_reg(hw_apbh_ch15_nxtcmdar) mx28_reg_32(hw_apbh_ch15_nxtcmdar)
mx28_reg(hw_apbh_ch15_cmd) mx28_reg_32(hw_apbh_ch15_cmd)
mx28_reg(hw_apbh_ch15_bar) mx28_reg_32(hw_apbh_ch15_bar)
mx28_reg(hw_apbh_ch15_sema) mx28_reg_32(hw_apbh_ch15_sema)
mx28_reg(hw_apbh_ch15_debug1) mx28_reg_32(hw_apbh_ch15_debug1)
mx28_reg(hw_apbh_ch15_debug2) mx28_reg_32(hw_apbh_ch15_debug2)
}; };
}; };
mx28_reg(hw_apbh_version) mx28_reg_32(hw_apbh_version)
}; };
#endif #endif

42
arch/arm/include/asm/arch-mx28/regs-bch.h
View File

@ -30,30 +30,30 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_bch_regs { struct mx28_bch_regs {
mx28_reg(hw_bch_ctrl) mx28_reg_32(hw_bch_ctrl)
mx28_reg(hw_bch_status0) mx28_reg_32(hw_bch_status0)
mx28_reg(hw_bch_mode) mx28_reg_32(hw_bch_mode)
mx28_reg(hw_bch_encodeptr) mx28_reg_32(hw_bch_encodeptr)
mx28_reg(hw_bch_dataptr) mx28_reg_32(hw_bch_dataptr)
mx28_reg(hw_bch_metaptr) mx28_reg_32(hw_bch_metaptr)
uint32_t reserved[4]; uint32_t reserved[4];
mx28_reg(hw_bch_layoutselect) mx28_reg_32(hw_bch_layoutselect)
mx28_reg(hw_bch_flash0layout0) mx28_reg_32(hw_bch_flash0layout0)
mx28_reg(hw_bch_flash0layout1) mx28_reg_32(hw_bch_flash0layout1)
mx28_reg(hw_bch_flash1layout0) mx28_reg_32(hw_bch_flash1layout0)
mx28_reg(hw_bch_flash1layout1) mx28_reg_32(hw_bch_flash1layout1)
mx28_reg(hw_bch_flash2layout0) mx28_reg_32(hw_bch_flash2layout0)
mx28_reg(hw_bch_flash2layout1) mx28_reg_32(hw_bch_flash2layout1)
mx28_reg(hw_bch_flash3layout0) mx28_reg_32(hw_bch_flash3layout0)
mx28_reg(hw_bch_flash3layout1) mx28_reg_32(hw_bch_flash3layout1)
mx28_reg(hw_bch_dbgkesread) mx28_reg_32(hw_bch_dbgkesread)
mx28_reg(hw_bch_dbgcsferead) mx28_reg_32(hw_bch_dbgcsferead)
mx28_reg(hw_bch_dbgsyndegread) mx28_reg_32(hw_bch_dbgsyndegread)
mx28_reg(hw_bch_dbgahbmread) mx28_reg_32(hw_bch_dbgahbmread)
mx28_reg(hw_bch_blockname) mx28_reg_32(hw_bch_blockname)
mx28_reg(hw_bch_version) mx28_reg_32(hw_bch_version)
}; };
#endif #endif

58
arch/arm/include/asm/arch-mx28/regs-clkctrl.h
View File

@ -30,38 +30,38 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_clkctrl_regs { struct mx28_clkctrl_regs {
mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */ mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */ mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */ mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */ mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */ mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
mx28_reg(hw_clkctrl_cpu) /* 0x50 */ mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */
mx28_reg(hw_clkctrl_hbus) /* 0x60 */ mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */
mx28_reg(hw_clkctrl_xbus) /* 0x70 */ mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */
mx28_reg(hw_clkctrl_xtal) /* 0x80 */ mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */
mx28_reg(hw_clkctrl_ssp0) /* 0x90 */ mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */
mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */ mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */ mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */ mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */ mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
mx28_reg(hw_clkctrl_spdif) /* 0xe0 */ mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */
mx28_reg(hw_clkctrl_emi) /* 0xf0 */ mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */
mx28_reg(hw_clkctrl_saif0) /* 0x100 */ mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */
mx28_reg(hw_clkctrl_saif1) /* 0x110 */ mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */
mx28_reg(hw_clkctrl_lcdif) /* 0x120 */ mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */
mx28_reg(hw_clkctrl_etm) /* 0x130 */ mx28_reg_32(hw_clkctrl_etm) /* 0x130 */
mx28_reg(hw_clkctrl_enet) /* 0x140 */ mx28_reg_32(hw_clkctrl_enet) /* 0x140 */
mx28_reg(hw_clkctrl_hsadc) /* 0x150 */ mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */
mx28_reg(hw_clkctrl_flexcan) /* 0x160 */ mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */
uint32_t reserved[16]; uint32_t reserved[16];
mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */ mx28_reg_32(hw_clkctrl_frac0) /* 0x1b0 */
mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */ mx28_reg_32(hw_clkctrl_frac1) /* 0x1c0 */
mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */ mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
mx28_reg(hw_clkctrl_reset) /* 0x1e0 */ mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */
mx28_reg(hw_clkctrl_status) /* 0x1f0 */ mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */
mx28_reg(hw_clkctrl_version) /* 0x200 */ mx28_reg_32(hw_clkctrl_version) /* 0x200 */
}; };
#endif #endif

12
arch/arm/include/asm/arch-mx28/regs-common.h
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@ -47,20 +47,20 @@
* *
*/ */
#define __mx28_reg(name) \ #define __mx28_reg_32(name) \
uint32_t name; \ uint32_t name; \
uint32_t name##_set; \ uint32_t name##_set; \
uint32_t name##_clr; \ uint32_t name##_clr; \
uint32_t name##_tog; uint32_t name##_tog;
struct mx28_register { struct mx28_register_32 {
__mx28_reg(reg) __mx28_reg_32(reg)
}; };
#define mx28_reg(name) \ #define mx28_reg_32(name) \
union { \ union { \
struct { __mx28_reg(name) }; \ struct { __mx28_reg_32(name) }; \
struct mx28_register name##_reg; \ struct mx28_register_32 name##_reg; \
}; };
#endif /* __MX28_REGS_COMMON_H__ */ #endif /* __MX28_REGS_COMMON_H__ */

26
arch/arm/include/asm/arch-mx28/regs-gpmi.h
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@ -30,22 +30,22 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_gpmi_regs { struct mx28_gpmi_regs {
mx28_reg(hw_gpmi_ctrl0) mx28_reg_32(hw_gpmi_ctrl0)
mx28_reg(hw_gpmi_compare) mx28_reg_32(hw_gpmi_compare)
mx28_reg(hw_gpmi_eccctrl) mx28_reg_32(hw_gpmi_eccctrl)
mx28_reg(hw_gpmi_ecccount) mx28_reg_32(hw_gpmi_ecccount)
mx28_reg(hw_gpmi_payload) mx28_reg_32(hw_gpmi_payload)
mx28_reg(hw_gpmi_auxiliary) mx28_reg_32(hw_gpmi_auxiliary)
mx28_reg(hw_gpmi_ctrl1) mx28_reg_32(hw_gpmi_ctrl1)
mx28_reg(hw_gpmi_timing0) mx28_reg_32(hw_gpmi_timing0)
mx28_reg(hw_gpmi_timing1) mx28_reg_32(hw_gpmi_timing1)
uint32_t reserved[4]; uint32_t reserved[4];
mx28_reg(hw_gpmi_data) mx28_reg_32(hw_gpmi_data)
mx28_reg(hw_gpmi_stat) mx28_reg_32(hw_gpmi_stat)
mx28_reg(hw_gpmi_debug) mx28_reg_32(hw_gpmi_debug)
mx28_reg(hw_gpmi_version) mx28_reg_32(hw_gpmi_version)
}; };
#endif #endif

28
arch/arm/include/asm/arch-mx28/regs-i2c.h
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@ -27,20 +27,20 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_i2c_regs { struct mx28_i2c_regs {
mx28_reg(hw_i2c_ctrl0) mx28_reg_32(hw_i2c_ctrl0)
mx28_reg(hw_i2c_timing0) mx28_reg_32(hw_i2c_timing0)
mx28_reg(hw_i2c_timing1) mx28_reg_32(hw_i2c_timing1)
mx28_reg(hw_i2c_timing2) mx28_reg_32(hw_i2c_timing2)
mx28_reg(hw_i2c_ctrl1) mx28_reg_32(hw_i2c_ctrl1)
mx28_reg(hw_i2c_stat) mx28_reg_32(hw_i2c_stat)
mx28_reg(hw_i2c_queuectrl) mx28_reg_32(hw_i2c_queuectrl)
mx28_reg(hw_i2c_queuestat) mx28_reg_32(hw_i2c_queuestat)
mx28_reg(hw_i2c_queuecmd) mx28_reg_32(hw_i2c_queuecmd)
mx28_reg(hw_i2c_queuedata) mx28_reg_32(hw_i2c_queuedata)
mx28_reg(hw_i2c_data) mx28_reg_32(hw_i2c_data)
mx28_reg(hw_i2c_debug0) mx28_reg_32(hw_i2c_debug0)
mx28_reg(hw_i2c_debug1) mx28_reg_32(hw_i2c_debug1)
mx28_reg(hw_i2c_version) mx28_reg_32(hw_i2c_version)
}; };
#endif #endif

86
arch/arm/include/asm/arch-mx28/regs-ocotp.h
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@ -30,49 +30,49 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_ocotp_regs { struct mx28_ocotp_regs {
mx28_reg(hw_ocotp_ctrl) /* 0x0 */ mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */
mx28_reg(hw_ocotp_data) /* 0x10 */ mx28_reg_32(hw_ocotp_data) /* 0x10 */
mx28_reg(hw_ocotp_cust0) /* 0x20 */ mx28_reg_32(hw_ocotp_cust0) /* 0x20 */
mx28_reg(hw_ocotp_cust1) /* 0x30 */ mx28_reg_32(hw_ocotp_cust1) /* 0x30 */
mx28_reg(hw_ocotp_cust2) /* 0x40 */ mx28_reg_32(hw_ocotp_cust2) /* 0x40 */
mx28_reg(hw_ocotp_cust3) /* 0x50 */ mx28_reg_32(hw_ocotp_cust3) /* 0x50 */
mx28_reg(hw_ocotp_crypto0) /* 0x60 */ mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */
mx28_reg(hw_ocotp_crypto1) /* 0x70 */ mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */
mx28_reg(hw_ocotp_crypto2) /* 0x80 */ mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */
mx28_reg(hw_ocotp_crypto3) /* 0x90 */ mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */
mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */ mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */ mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */ mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */ mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */ mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */ mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
mx28_reg(hw_ocotp_swcap) /* 0x100 */ mx28_reg_32(hw_ocotp_swcap) /* 0x100 */
mx28_reg(hw_ocotp_custcap) /* 0x110 */ mx28_reg_32(hw_ocotp_custcap) /* 0x110 */
mx28_reg(hw_ocotp_lock) /* 0x120 */ mx28_reg_32(hw_ocotp_lock) /* 0x120 */
mx28_reg(hw_ocotp_ops0) /* 0x130 */ mx28_reg_32(hw_ocotp_ops0) /* 0x130 */
mx28_reg(hw_ocotp_ops1) /* 0x140 */ mx28_reg_32(hw_ocotp_ops1) /* 0x140 */
mx28_reg(hw_ocotp_ops2) /* 0x150 */ mx28_reg_32(hw_ocotp_ops2) /* 0x150 */
mx28_reg(hw_ocotp_ops3) /* 0x160 */ mx28_reg_32(hw_ocotp_ops3) /* 0x160 */
mx28_reg(hw_ocotp_un0) /* 0x170 */ mx28_reg_32(hw_ocotp_un0) /* 0x170 */
mx28_reg(hw_ocotp_un1) /* 0x180 */ mx28_reg_32(hw_ocotp_un1) /* 0x180 */
mx28_reg(hw_ocotp_un2) /* 0x190 */ mx28_reg_32(hw_ocotp_un2) /* 0x190 */
mx28_reg(hw_ocotp_rom0) /* 0x1a0 */ mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */
mx28_reg(hw_ocotp_rom1) /* 0x1b0 */ mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */
mx28_reg(hw_ocotp_rom2) /* 0x1c0 */ mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */
mx28_reg(hw_ocotp_rom3) /* 0x1d0 */ mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */
mx28_reg(hw_ocotp_rom4) /* 0x1e0 */ mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */
mx28_reg(hw_ocotp_rom5) /* 0x1f0 */ mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */
mx28_reg(hw_ocotp_rom6) /* 0x200 */ mx28_reg_32(hw_ocotp_rom6) /* 0x200 */
mx28_reg(hw_ocotp_rom7) /* 0x210 */ mx28_reg_32(hw_ocotp_rom7) /* 0x210 */
mx28_reg(hw_ocotp_srk0) /* 0x220 */ mx28_reg_32(hw_ocotp_srk0) /* 0x220 */
mx28_reg(hw_ocotp_srk1) /* 0x230 */ mx28_reg_32(hw_ocotp_srk1) /* 0x230 */
mx28_reg(hw_ocotp_srk2) /* 0x240 */ mx28_reg_32(hw_ocotp_srk2) /* 0x240 */
mx28_reg(hw_ocotp_srk3) /* 0x250 */ mx28_reg_32(hw_ocotp_srk3) /* 0x250 */
mx28_reg(hw_ocotp_srk4) /* 0x260 */ mx28_reg_32(hw_ocotp_srk4) /* 0x260 */
mx28_reg(hw_ocotp_srk5) /* 0x270 */ mx28_reg_32(hw_ocotp_srk5) /* 0x270 */
mx28_reg(hw_ocotp_srk6) /* 0x280 */ mx28_reg_32(hw_ocotp_srk6) /* 0x280 */
mx28_reg(hw_ocotp_srk7) /* 0x290 */ mx28_reg_32(hw_ocotp_srk7) /* 0x290 */
mx28_reg(hw_ocotp_version) /* 0x2a0 */ mx28_reg_32(hw_ocotp_version) /* 0x2a0 */
}; };
#endif #endif

168
arch/arm/include/asm/arch-mx28/regs-pinctrl.h
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@ -30,129 +30,129 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_pinctrl_regs { struct mx28_pinctrl_regs {
mx28_reg(hw_pinctrl_ctrl) /* 0x0 */ mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */
uint32_t reserved1[60]; uint32_t reserved1[60];
mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */ mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */ mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */ mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */ mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */ mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */ mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */ mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */ mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */ mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */ mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */ mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */ mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */ mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */ mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
uint32_t reserved2[72]; uint32_t reserved2[72];
mx28_reg(hw_pinctrl_drive0) /* 0x300 */ mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */
mx28_reg(hw_pinctrl_drive1) /* 0x310 */ mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */
mx28_reg(hw_pinctrl_drive2) /* 0x320 */ mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */
mx28_reg(hw_pinctrl_drive3) /* 0x330 */ mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */
mx28_reg(hw_pinctrl_drive4) /* 0x340 */ mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */
mx28_reg(hw_pinctrl_drive5) /* 0x350 */ mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */
mx28_reg(hw_pinctrl_drive6) /* 0x360 */ mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */
mx28_reg(hw_pinctrl_drive7) /* 0x370 */ mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */
mx28_reg(hw_pinctrl_drive8) /* 0x380 */ mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */
mx28_reg(hw_pinctrl_drive9) /* 0x390 */ mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */
mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */ mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */ mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */ mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */ mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */ mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */ mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
mx28_reg(hw_pinctrl_drive16) /* 0x400 */ mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */
mx28_reg(hw_pinctrl_drive17) /* 0x410 */ mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */
mx28_reg(hw_pinctrl_drive18) /* 0x420 */ mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */
mx28_reg(hw_pinctrl_drive19) /* 0x430 */ mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */
uint32_t reserved3[112]; uint32_t reserved3[112];
mx28_reg(hw_pinctrl_pull0) /* 0x600 */ mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */
mx28_reg(hw_pinctrl_pull1) /* 0x610 */ mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */
mx28_reg(hw_pinctrl_pull2) /* 0x620 */ mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */
mx28_reg(hw_pinctrl_pull3) /* 0x630 */ mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */
mx28_reg(hw_pinctrl_pull4) /* 0x640 */ mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */
mx28_reg(hw_pinctrl_pull5) /* 0x650 */ mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */
mx28_reg(hw_pinctrl_pull6) /* 0x660 */ mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */
uint32_t reserved4[36]; uint32_t reserved4[36];
mx28_reg(hw_pinctrl_dout0) /* 0x700 */ mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */
mx28_reg(hw_pinctrl_dout1) /* 0x710 */ mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */
mx28_reg(hw_pinctrl_dout2) /* 0x720 */ mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */
mx28_reg(hw_pinctrl_dout3) /* 0x730 */ mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */
mx28_reg(hw_pinctrl_dout4) /* 0x740 */ mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */
uint32_t reserved5[108]; uint32_t reserved5[108];
mx28_reg(hw_pinctrl_din0) /* 0x900 */ mx28_reg_32(hw_pinctrl_din0) /* 0x900 */
mx28_reg(hw_pinctrl_din1) /* 0x910 */ mx28_reg_32(hw_pinctrl_din1) /* 0x910 */
mx28_reg(hw_pinctrl_din2) /* 0x920 */ mx28_reg_32(hw_pinctrl_din2) /* 0x920 */
mx28_reg(hw_pinctrl_din3) /* 0x930 */ mx28_reg_32(hw_pinctrl_din3) /* 0x930 */
mx28_reg(hw_pinctrl_din4) /* 0x940 */ mx28_reg_32(hw_pinctrl_din4) /* 0x940 */
uint32_t reserved6[108]; uint32_t reserved6[108];
mx28_reg(hw_pinctrl_doe0) /* 0xb00 */ mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */
mx28_reg(hw_pinctrl_doe1) /* 0xb10 */ mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */
mx28_reg(hw_pinctrl_doe2) /* 0xb20 */ mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */
mx28_reg(hw_pinctrl_doe3) /* 0xb30 */ mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */
mx28_reg(hw_pinctrl_doe4) /* 0xb40 */ mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */
uint32_t reserved7[300]; uint32_t reserved7[300];
mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */ mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */ mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */ mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */ mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */ mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
uint32_t reserved8[44]; uint32_t reserved8[44];
mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */ mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */ mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */ mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */ mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */ mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
uint32_t reserved9[44]; uint32_t reserved9[44];
mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */ mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */ mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */ mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */ mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */ mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
uint32_t reserved10[44]; uint32_t reserved10[44];
mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */ mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */ mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */ mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */ mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */ mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
uint32_t reserved11[44]; uint32_t reserved11[44];
mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */ mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */ mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */ mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */ mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */ mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
uint32_t reserved12[380]; uint32_t reserved12[380];
mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
uint32_t reserved13[76]; uint32_t reserved13[76];
mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
}; };
#endif #endif

28
arch/arm/include/asm/arch-mx28/regs-power.h
View File

@ -26,10 +26,10 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_power_regs { struct mx28_power_regs {
mx28_reg(hw_power_ctrl) mx28_reg_32(hw_power_ctrl)
mx28_reg(hw_power_5vctrl) mx28_reg_32(hw_power_5vctrl)
mx28_reg(hw_power_minpwr) mx28_reg_32(hw_power_minpwr)
mx28_reg(hw_power_charge) mx28_reg_32(hw_power_charge)
uint32_t hw_power_vdddctrl; uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3]; uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl; uint32_t hw_power_vddactrl;
@ -44,23 +44,23 @@ struct mx28_power_regs {
uint32_t reserved_misc[3]; uint32_t reserved_misc[3];
uint32_t hw_power_dclimits; uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3]; uint32_t reserved_dclimits[3];
mx28_reg(hw_power_loopctrl) mx28_reg_32(hw_power_loopctrl)
uint32_t hw_power_sts; uint32_t hw_power_sts;
uint32_t reserved_sts[3]; uint32_t reserved_sts[3];
mx28_reg(hw_power_speed) mx28_reg_32(hw_power_speed)
uint32_t hw_power_battmonitor; uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3]; uint32_t reserved_battmonitor[3];
uint32_t reserved[4]; uint32_t reserved[4];
mx28_reg(hw_power_reset) mx28_reg_32(hw_power_reset)
mx28_reg(hw_power_debug) mx28_reg_32(hw_power_debug)
mx28_reg(hw_power_thermal) mx28_reg_32(hw_power_thermal)
mx28_reg(hw_power_usb1ctrl) mx28_reg_32(hw_power_usb1ctrl)
mx28_reg(hw_power_special) mx28_reg_32(hw_power_special)
mx28_reg(hw_power_version) mx28_reg_32(hw_power_version)
mx28_reg(hw_power_anaclkctrl) mx28_reg_32(hw_power_anaclkctrl)
mx28_reg(hw_power_refctrl) mx28_reg_32(hw_power_refctrl)
}; };
#endif #endif

28
arch/arm/include/asm/arch-mx28/regs-rtc.h
View File

@ -27,20 +27,20 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_rtc_regs { struct mx28_rtc_regs {
mx28_reg(hw_rtc_ctrl) mx28_reg_32(hw_rtc_ctrl)
mx28_reg(hw_rtc_stat) mx28_reg_32(hw_rtc_stat)
mx28_reg(hw_rtc_milliseconds) mx28_reg_32(hw_rtc_milliseconds)
mx28_reg(hw_rtc_seconds) mx28_reg_32(hw_rtc_seconds)
mx28_reg(hw_rtc_rtc_alarm) mx28_reg_32(hw_rtc_rtc_alarm)
mx28_reg(hw_rtc_watchdog) mx28_reg_32(hw_rtc_watchdog)
mx28_reg(hw_rtc_persistent0) mx28_reg_32(hw_rtc_persistent0)
mx28_reg(hw_rtc_persistent1) mx28_reg_32(hw_rtc_persistent1)
mx28_reg(hw_rtc_persistent2) mx28_reg_32(hw_rtc_persistent2)
mx28_reg(hw_rtc_persistent3) mx28_reg_32(hw_rtc_persistent3)
mx28_reg(hw_rtc_persistent4) mx28_reg_32(hw_rtc_persistent4)
mx28_reg(hw_rtc_persistent5) mx28_reg_32(hw_rtc_persistent5)
mx28_reg(hw_rtc_debug) mx28_reg_32(hw_rtc_debug)
mx28_reg(hw_rtc_version) mx28_reg_32(hw_rtc_version)
}; };
#endif #endif

40
arch/arm/include/asm/arch-mx28/regs-ssp.h
View File

@ -29,26 +29,26 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_ssp_regs { struct mx28_ssp_regs {
mx28_reg(hw_ssp_ctrl0) mx28_reg_32(hw_ssp_ctrl0)
mx28_reg(hw_ssp_cmd0) mx28_reg_32(hw_ssp_cmd0)
mx28_reg(hw_ssp_cmd1) mx28_reg_32(hw_ssp_cmd1)
mx28_reg(hw_ssp_xfer_size) mx28_reg_32(hw_ssp_xfer_size)
mx28_reg(hw_ssp_block_size) mx28_reg_32(hw_ssp_block_size)
mx28_reg(hw_ssp_compref) mx28_reg_32(hw_ssp_compref)
mx28_reg(hw_ssp_compmask) mx28_reg_32(hw_ssp_compmask)
mx28_reg(hw_ssp_timing) mx28_reg_32(hw_ssp_timing)
mx28_reg(hw_ssp_ctrl1) mx28_reg_32(hw_ssp_ctrl1)
mx28_reg(hw_ssp_data) mx28_reg_32(hw_ssp_data)
mx28_reg(hw_ssp_sdresp0) mx28_reg_32(hw_ssp_sdresp0)
mx28_reg(hw_ssp_sdresp1) mx28_reg_32(hw_ssp_sdresp1)
mx28_reg(hw_ssp_sdresp2) mx28_reg_32(hw_ssp_sdresp2)
mx28_reg(hw_ssp_sdresp3) mx28_reg_32(hw_ssp_sdresp3)
mx28_reg(hw_ssp_ddr_ctrl) mx28_reg_32(hw_ssp_ddr_ctrl)
mx28_reg(hw_ssp_dll_ctrl) mx28_reg_32(hw_ssp_dll_ctrl)
mx28_reg(hw_ssp_status) mx28_reg_32(hw_ssp_status)
mx28_reg(hw_ssp_dll_sts) mx28_reg_32(hw_ssp_dll_sts)
mx28_reg(hw_ssp_debug) mx28_reg_32(hw_ssp_debug)
mx28_reg(hw_ssp_version) mx28_reg_32(hw_ssp_version)
}; };
#endif #endif

38
arch/arm/include/asm/arch-mx28/regs-timrot.h
View File

@ -29,25 +29,25 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
struct mx28_timrot_regs { struct mx28_timrot_regs {
mx28_reg(hw_timrot_rotctrl) mx28_reg_32(hw_timrot_rotctrl)
mx28_reg(hw_timrot_rotcount) mx28_reg_32(hw_timrot_rotcount)
mx28_reg(hw_timrot_timctrl0) mx28_reg_32(hw_timrot_timctrl0)
mx28_reg(hw_timrot_running_count0) mx28_reg_32(hw_timrot_running_count0)
mx28_reg(hw_timrot_fixed_count0) mx28_reg_32(hw_timrot_fixed_count0)
mx28_reg(hw_timrot_match_count0) mx28_reg_32(hw_timrot_match_count0)
mx28_reg(hw_timrot_timctrl1) mx28_reg_32(hw_timrot_timctrl1)
mx28_reg(hw_timrot_running_count1) mx28_reg_32(hw_timrot_running_count1)
mx28_reg(hw_timrot_fixed_count1) mx28_reg_32(hw_timrot_fixed_count1)
mx28_reg(hw_timrot_match_count1) mx28_reg_32(hw_timrot_match_count1)
mx28_reg(hw_timrot_timctrl2) mx28_reg_32(hw_timrot_timctrl2)
mx28_reg(hw_timrot_running_count2) mx28_reg_32(hw_timrot_running_count2)
mx28_reg(hw_timrot_fixed_count2) mx28_reg_32(hw_timrot_fixed_count2)
mx28_reg(hw_timrot_match_count2) mx28_reg_32(hw_timrot_match_count2)
mx28_reg(hw_timrot_timctrl3) mx28_reg_32(hw_timrot_timctrl3)
mx28_reg(hw_timrot_running_count3) mx28_reg_32(hw_timrot_running_count3)
mx28_reg(hw_timrot_fixed_count3) mx28_reg_32(hw_timrot_fixed_count3)
mx28_reg(hw_timrot_match_count3) mx28_reg_32(hw_timrot_match_count3)
mx28_reg(hw_timrot_version) mx28_reg_32(hw_timrot_version)
}; };
#endif #endif

20
arch/arm/include/asm/arch-mx28/regs-usbphy.h
View File

@ -24,16 +24,16 @@
#define __REGS_USBPHY_H__ #define __REGS_USBPHY_H__
struct mx28_usbphy_regs { struct mx28_usbphy_regs {
mx28_reg(hw_usbphy_pwd) mx28_reg_32(hw_usbphy_pwd)
mx28_reg(hw_usbphy_tx) mx28_reg_32(hw_usbphy_tx)
mx28_reg(hw_usbphy_rx) mx28_reg_32(hw_usbphy_rx)
mx28_reg(hw_usbphy_ctrl) mx28_reg_32(hw_usbphy_ctrl)
mx28_reg(hw_usbphy_status) mx28_reg_32(hw_usbphy_status)
mx28_reg(hw_usbphy_debug) mx28_reg_32(hw_usbphy_debug)
mx28_reg(hw_usbphy_debug0_status) mx28_reg_32(hw_usbphy_debug0_status)
mx28_reg(hw_usbphy_debug1) mx28_reg_32(hw_usbphy_debug1)
mx28_reg(hw_usbphy_version) mx28_reg_32(hw_usbphy_version)
mx28_reg(hw_usbphy_ip) mx28_reg_32(hw_usbphy_ip)
}; };
#define USBPHY_PWD_RXPWDRX (1 << 20) #define USBPHY_PWD_RXPWDRX (1 << 20)

10
arch/arm/include/asm/arch-mx28/sys_proto.h
View File

@ -23,9 +23,13 @@
#ifndef __MX28_H__ #ifndef __MX28_H__
#define __MX28_H__ #define __MX28_H__
int mx28_reset_block(struct mx28_register *reg); int mx28_reset_block(struct mx28_register_32 *reg);
int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout); int mx28_wait_mask_set(struct mx28_register_32 *reg,
int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout); uint32_t mask,
int timeout);
int mx28_wait_mask_clr(struct mx28_register_32 *reg,
uint32_t mask,
int timeout);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));

16
drivers/gpio/mxs_gpio.c
View File

@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio)
{ {
uint32_t bank = PAD_BANK(gpio); uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DIN(bank); uint32_t offset = PINCTRL_DIN(bank);
struct mx28_register *reg = struct mx28_register_32 *reg =
(struct mx28_register *)(MXS_PINCTRL_BASE + offset); (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1; return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
} }
@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value)
{ {
uint32_t bank = PAD_BANK(gpio); uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOUT(bank); uint32_t offset = PINCTRL_DOUT(bank);
struct mx28_register *reg = struct mx28_register_32 *reg =
(struct mx28_register *)(MXS_PINCTRL_BASE + offset); (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
if (value) if (value)
writel(1 << PAD_PIN(gpio), &reg->reg_set); writel(1 << PAD_PIN(gpio), &reg->reg_set);
@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio)
{ {
uint32_t bank = PAD_BANK(gpio); uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank); uint32_t offset = PINCTRL_DOE(bank);
struct mx28_register *reg = struct mx28_register_32 *reg =
(struct mx28_register *)(MXS_PINCTRL_BASE + offset); (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), &reg->reg_clr); writel(1 << PAD_PIN(gpio), &reg->reg_clr);
@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value)
{ {
uint32_t bank = PAD_BANK(gpio); uint32_t bank = PAD_BANK(gpio);
uint32_t offset = PINCTRL_DOE(bank); uint32_t offset = PINCTRL_DOE(bank);
struct mx28_register *reg = struct mx28_register_32 *reg =
(struct mx28_register *)(MXS_PINCTRL_BASE + offset); (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
writel(1 << PAD_PIN(gpio), &reg->reg_set); writel(1 << PAD_PIN(gpio), &reg->reg_set);

8
drivers/usb/host/ehci-mxs.c
View File

@ -75,8 +75,8 @@ int ehci_hcd_init(void)
int ret; int ret;
uint32_t usb_base, cap_base; uint32_t usb_base, cap_base;
struct mx28_register *digctl_ctrl = struct mx28_register_32 *digctl_ctrl =
(struct mx28_register *)HW_DIGCTL_CTRL; (struct mx28_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs = struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -119,8 +119,8 @@ int ehci_hcd_stop(void)
{ {
int ret; int ret;
uint32_t tmp; uint32_t tmp;
struct mx28_register *digctl_ctrl = struct mx28_register_32 *digctl_ctrl =
(struct mx28_register *)HW_DIGCTL_CTRL; (struct mx28_register_32 *)HW_DIGCTL_CTRL;
struct mx28_clkctrl_regs *clkctrl_regs = struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;