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S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)

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The source of pwm clock is fixed at evt1.
And some registers for pwm clock are removed.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Minkyu Kang 2011-05-18 16:57:55 +09:00
parent 68a8cbfad9
commit b4f73910d9
1 changed files with 25 additions and 19 deletions
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44
arch/arm/cpu/armv7/s5pc2xx/clock.c
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@ -124,29 +124,35 @@ static unsigned long s5pc210_get_pwm_clk(void)
unsigned int sel; unsigned int sel;
unsigned int ratio; unsigned int ratio;
/* if (s5p_get_cpu_rev() == 0) {
* CLK_SRC_PERIL0 /*
* PWM_SEL [27:24] * CLK_SRC_PERIL0
*/ * PWM_SEL [27:24]
sel = readl(&clk->src_peril0); */
sel = (sel >> 24) & 0xf; sel = readl(&clk->src_peril0);
sel = (sel >> 24) & 0xf;
if (sel == 0x6) if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
return 0;
/*
* CLK_DIV_PERIL3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peril3);
ratio = ratio & 0xf;
} else if (s5p_get_cpu_rev() == 1) {
sclk = get_pll_clk(MPLL); sclk = get_pll_clk(MPLL);
else if (sel == 0x7) ratio = 8;
sclk = get_pll_clk(EPLL); } else
else if (sel == 0x8)
sclk = get_pll_clk(VPLL);
else
return 0; return 0;
/*
* CLK_DIV_PERIL3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peril3);
ratio = ratio & 0xf;
pclk = sclk / (ratio + 1); pclk = sclk / (ratio + 1);
return pclk; return pclk;