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mpc83xx: cosmetic: SIMPC8313.h checkpatch compliance

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:21 -05:00 committed by Kim Phillips
parent b2773a5e1c
commit bb0f5bc92d
1 changed files with 163 additions and 123 deletions
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156
include/configs/SIMPC8313.h
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@ -88,17 +88,18 @@
/* /*
* DDR Setup * DDR Setup
*/ */
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ /* DDR is system memory*/
#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_VERY_BIG_RAM #define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (512 << 20) #define CONFIG_MAX_MEM_MAPPED (512 << 20)
#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ #define CONFIG_SYS_DDRCDR (DDRCDR_EN \
| DDRCDR_PZ_NOMZ \ | DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \ | DDRCDR_NZ_NOMZ \
| DDRCDR_M_ODR ) | DDRCDR_M_ODR)
/* 0x73000002 TODO ODR & DRN ? */ /* 0x73000002 TODO ODR & DRN ? */
/* /*
@ -114,7 +115,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
@ -129,9 +131,10 @@
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \ | (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */ | 0xF) /* 0x0004ff0f */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ /* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR 0x20000000
/* drivers/mtd/nand/nand.c */ /* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL #ifdef CONFIG_NAND_SPL
@ -147,36 +150,38 @@
#define CONFIG_CMD_NAND 1 #define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* 8 bit Port */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */ | BR_V) /* valid */
#ifdef CONFIG_NAND_SP #ifdef CONFIG_NAND_SP
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \ | OR_FCM_CSCT \
| OR_FCM_CST \ | OR_FCM_CST \
| OR_FCM_CHT \ | OR_FCM_CHT \
| OR_FCM_SCY_1 \ | OR_FCM_SCY_1 \
| OR_FCM_TRLX \ | OR_FCM_TRLX \
| OR_FCM_EHTR ) | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ /* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
#define NAND_CACHE_PAGES 32 #define NAND_CACHE_PAGES 32
#elif defined(CONFIG_NAND_LP) #elif defined(CONFIG_NAND_LP)
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS \ | OR_FCM_PGS \
| OR_FCM_CSCT \ | OR_FCM_CSCT \
| OR_FCM_CST \ | OR_FCM_CST \
| OR_FCM_CHT \ | OR_FCM_CHT \
| OR_FCM_SCY_1 \ | OR_FCM_SCY_1 \
| OR_FCM_TRLX \ | OR_FCM_TRLX \
| OR_FCM_EHTR ) | OR_FCM_EHTR)
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ /* NAND chip block size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
#define NAND_CACHE_PAGES 64 #define NAND_CACHE_PAGES 64
#else #else
#error Page size of NAND not defined. #error Page size of NAND not defined.
@ -192,11 +197,11 @@
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \ #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
| BR_PS_16 \ | BR_PS_16 \
| BR_MS_UPMA \ | BR_MS_UPMA \
| BR_V ) | BR_V)
#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \ #define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
| OR_UPM_BCTLD) | OR_UPM_BCTLD)
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
@ -246,7 +251,7 @@
#define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C2_OFFSET 0x3100
@ -312,10 +317,12 @@
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) #define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT) #elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SIZE 0x2000
@ -369,11 +376,12 @@
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) \ + sizeof(CONFIG_SYS_PROMPT) \
+ 16 ) /* Print Buffer Size */ + 16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/* /*
@ -381,19 +389,20 @@
* have to be in the first 256 MB of memory, since this is * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization. * the maximum mapped by the Linux kernel during initialization.
*/ */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ #define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
| 0x20000000 /* reserved */ \ | 0x20000000 /* reserved */ \
| HRCWL_DDR_TO_SCB_CLK_2X1 \ | HRCWL_DDR_TO_SCB_CLK_2X1 \
| HRCWL_CSB_TO_CLKIN_4X1 \ | HRCWL_CSB_TO_CLKIN_4X1 \
| HRCWL_CORE_TO_CSB_2_5X1 ) | HRCWL_CORE_TO_CSB_2_5X1)
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ #define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
| HRCWH_PCI1_ARBITER_ENABLE \ | HRCWH_PCI1_ARBITER_ENABLE \
| HRCWH_CORE_ENABLE \ | HRCWH_CORE_ENABLE \
| HRCWH_BOOTSEQ_DISABLE \ | HRCWH_BOOTSEQ_DISABLE \
@ -401,37 +410,37 @@
| HRCWH_TSEC1M_IN_RGMII \ | HRCWH_TSEC1M_IN_RGMII \
| HRCWH_TSEC2M_IN_RGMII \ | HRCWH_TSEC2M_IN_RGMII \
| HRCWH_BIG_ENDIAN \ | HRCWH_BIG_ENDIAN \
| HRCWH_LALE_NORMAL ) | HRCWH_LALE_NORMAL)
#ifdef CONFIG_NAND_LP #ifdef CONFIG_NAND_LP
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
| HRCWH_FROM_0XFFF00100 \ | HRCWH_FROM_0XFFF00100 \
| HRCWH_ROM_LOC_NAND_LP_8BIT \ | HRCWH_ROM_LOC_NAND_LP_8BIT \
| HRCWH_RL_EXT_NAND) | HRCWH_RL_EXT_NAND)
#else #else
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
| HRCWH_FROM_0XFFF00100 \ | HRCWH_FROM_0XFFF00100 \
| HRCWH_ROM_LOC_NAND_SP_8BIT \ | HRCWH_ROM_LOC_NAND_SP_8BIT \
| HRCWH_RL_EXT_NAND ) | HRCWH_RL_EXT_NAND)
#endif #endif
/* System IO Config */ /* System IO Config */
#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ #define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
| SICRH_ETSEC2_C \ | SICRH_ETSEC2_C \
| SICRH_ETSEC2_D \ | SICRH_ETSEC2_D \
| SICRH_ETSEC2_E \ | SICRH_ETSEC2_E \
| SICRH_ETSEC2_F \ | SICRH_ETSEC2_F \
| SICRH_ETSEC2_G \ | SICRH_ETSEC2_G \
| SICRH_TSOBI1 \ | SICRH_TSOBI1 \
| SICRH_TSOBI2 ) | SICRH_TSOBI2)
#define CONFIG_SYS_SICRL ( SICRL_LBC \ #define CONFIG_SYS_SICRL (SICRL_LBC \
| SICRL_USBDR_10 \ | SICRL_USBDR_10 \
| SICRL_ETSEC2_A ) | SICRL_ETSEC2_A)
#define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
HID0_ENABLE_INSTRUCTION_CACHE | \ | HID0_ENABLE_INSTRUCTION_CACHE \
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_SYS_HID2 HID2_HBE
@ -439,27 +448,54 @@
/* DDR @ 0x00000000 */ /* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) | BATU_BL_256M \
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) | BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
| BATL_PP_10)
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI @ 0x80000000 */ /* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATU_BL_256M \
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI2 not supported on 8313 */ /* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L (0) #define CONFIG_SYS_IBAT4L (0)
#define CONFIG_SYS_IBAT4U (0) #define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6L (0xF0000000 \
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT7L (0) #define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0) #define CONFIG_SYS_IBAT7U (0)
@ -486,27 +522,30 @@
*/ */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
#define CONFIG_NETDEV eth1 #define CONFIG_NETDEV "eth1"
#define CONFIG_HOSTNAME simpc8313 #define CONFIG_HOSTNAME simpc8313
#define CONFIG_ROOTPATH "/tftpboot/" #define CONFIG_ROOTPATH "/tftpboot/"
#define CONFIG_BOOTFILE "/tftpboot/uImage" #define CONFIG_BOOTFILE "/tftpboot/uImage"
#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ /* U-Boot image on TFTP server */
#define CONFIG_FDTFILE simpc8313.dtb #define CONFIG_UBOOTPATH "u-boot-nand.bin"
#define CONFIG_FDTFILE "simpc8313.dtb"
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ /* default location for tftp and bootm */
#define CONFIG_LOADADDR 500000
#define CONFIG_BOOTDELAY 5 /* 5 second delay */ #define CONFIG_BOOTDELAY 5 /* 5 second delay */
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
"bootm $loadaddr - $fdtaddr"
#define XMK_STR(x) #x #define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x) #define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \ "ethprime=TSEC1\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \ "tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
@ -514,12 +553,13 @@
"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"fdtaddr=ae0000\0" \ "fdtaddr=ae0000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \ "console=ttyS0\0" \
"setbootargs=setenv bootargs " \ "setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"load_uboot=tftp 100000 u-boot-nand.bin\0" \ "load_uboot=tftp 100000 u-boot-nand.bin\0" \
"burn_uboot=nand erase u-boot 80000; " \ "burn_uboot=nand erase u-boot 80000; " \