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EXYNOS: Clock: Add common function for pll rate calculation

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Moved the common code to calculate pll clock rate to new function
exynos_get_pll_clk().

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
This commit is contained in:
Minkyu Kang 2012-10-15 01:58:00 +00:00
parent 6fcc059f81
commit bb6527bc73
1 changed files with 38 additions and 64 deletions
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102
arch/arm/cpu/armv7/exynos/clock.c
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@ -26,41 +26,19 @@
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/clk.h> #include <asm/arch/clk.h>
/* exynos4: return pll clock frequency */ /* exynos: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg) static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{ {
struct exynos4_clock *clk = unsigned long m, p, s = 0, mask, fout;
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq; unsigned int freq;
switch (pllreg) {
case APLL:
r = readl(&clk->apll_con0);
break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
k = readl(&clk->epll_con1);
break;
case VPLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
/* /*
* APLL_CON: MIDV [25:16] * APLL_CON: MIDV [25:16]
* MPLL_CON: MIDV [25:16] * MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16] * EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]: Exynos5
*/ */
if (pllreg == APLL || pllreg == MPLL) if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff; mask = 0x3ff;
else else
mask = 0x1ff; mask = 0x1ff;
@ -92,13 +70,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
return fout; return fout;
} }
/* exynos4: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long r, k = 0;
switch (pllreg) {
case APLL:
r = readl(&clk->apll_con0);
break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
k = readl(&clk->epll_con1);
break;
case VPLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
return exynos_get_pll_clk(pllreg, r, k);
}
/* exynos5: return pll clock frequency */ /* exynos5: return pll clock frequency */
static unsigned long exynos5_get_pll_clk(int pllreg) static unsigned long exynos5_get_pll_clk(int pllreg)
{ {
struct exynos5_clock *clk = struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock(); (struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout; unsigned long r, k = 0, fout;
unsigned int freq, pll_div2_sel, fout_sel; unsigned int pll_div2_sel, fout_sel;
switch (pllreg) { switch (pllreg) {
case APLL: case APLL:
@ -123,41 +131,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return 0; return 0;
} }
/* fout = exynos_get_pll_clk(pllreg, r, k);
* APLL_CON: MIDV [25:16]
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]
*/
if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
m = (r >> 16) & mask;
/* PDIV [13:8] */
p = (r >> 8) & 0x3f;
/* SDIV [2:0] */
s = r & 0x7;
freq = CONFIG_SYS_CLK_FREQ;
if (pllreg == EPLL) {
k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 65536) * (freq / (p * (1 << s)));
} else if (pllreg == VPLL) {
k = k & 0xfff;
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 1024) * (freq / (p * (1 << s)));
} else {
if (s < 1)
s = 1;
/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
fout = m * (freq / (p * (1 << (s - 1))));
}
/* According to the user manual, in EVT1 MPLL and BPLL always gives /* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/