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ppc: Fix roll over bug in flush_cache()

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If we call flush_cache(0xfffff000, 0x1000) it would never
terminate the loop since end = 0xffffffff and we'd roll over
our counter from 0xfffffe0 to 0 (assuming a 32-byte cache line)

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-02-06 08:08:06 -06:00 committed by Wolfgang Denk
parent 87c9063963
commit bced7ccefa
1 changed files with 4 additions and 2 deletions
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6
lib_ppc/cache.c
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@ -33,14 +33,16 @@ void flush_cache(ulong start_addr, ulong size)
start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
end = start_addr + size - 1; end = start_addr + size - 1;
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { for (addr = start; (addr <= end) && (addr >= start);
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET(); WATCHDOG_RESET();
} }
/* wait for all dcbst to complete on bus */ /* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory"); asm volatile("sync" : : : "memory");
for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { for (addr = start; (addr <= end) && (addr >= start);
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
WATCHDOG_RESET(); WATCHDOG_RESET();
} }