minix/u-boot
1
0
Fork 0
mirror of https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git synced 2025-09-10 12:39:22 -04:00
Code Issues Packages Projects Releases Wiki Activity

mpc83xx: Add support for Errata DDR6 on MPC 834x systems

Browse Source 
CHANGELOG:

* Errata DDR6, which affects all current MPC 834x processors, lists changes
  required to maintain compatibility with various types of DDR memory.  This
  patch implements those changes.

Signed-off-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
Timur Tabi 2006-10-31 18:13:36 -06:00 committed by Kim Phillips
parent afd6e470f6
commit bed85caf87
1 changed files with 42 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
cpu/mpc83xx/spd_sdram.c
View File

@ -112,11 +112,14 @@ static void spd_debug(spd_eeprom_t *spd)
long int spd_sdram() long int spd_sdram()
{ {
#ifdef CONFIG_MPC834X
int caslat_83xx; /* For Errata DDR6 */
#endif
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
volatile ddr83xx_t *ddr = &immap->ddr; volatile ddr83xx_t *ddr = &immap->ddr;
volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
spd_eeprom_t spd; spd_eeprom_t spd;
unsigned tmp; unsigned int tmp, tmp1;
unsigned int memsize; unsigned int memsize;
unsigned int law_size; unsigned int law_size;
unsigned char caslat, caslat_ctrl; unsigned char caslat, caslat_ctrl;
@ -282,6 +285,40 @@ long int spd_sdram()
} }
} }
#ifdef CONFIG_MPC834X
/* Errata DDR6
This errata affects all MPC8349E, MPC8343E and MPC8347E processors.
*/
if ((tmp1 >= 280) && (tmp1 < 350)) /* CSB=333 */
{
if (spd.mid[0] == 0x2c) {
/* Micron memory running at 333 MHz */
/* Chances are, U-Boot will crash before we get here,
but just in case, display a message and return error. */
printf("Micron DDR not supported at 333MHz CSB\n");
return 0;
} else if (spd.mid[0] == 0xad) {
printf("Hynix DDR does not require Errata DDR6\n");
} else {
/* enable 2 cycle Earlier for CL=2.5 or 3 */
ddr->debug_reg = 0x202c0000;
printf("Errata DDR6 (debug_reg=0x%x)\n", ddr->debug_reg);
}
caslat_83xx = caslat;
}
if ((tmp1 >= 230) && (tmp1 < 280)) { /* CSB=266 */
if (spd.mid[0] != 0x2c) /* non-Micron */
caslat_83xx = caslat - 1;
}
if ((tmp1 >= 90) && (tmp1 < 230)) { /* CSB=200 */
caslat = 3;
caslat_83xx = 2;
}
#endif
/* /*
* note: caslat must also be programmed into ddr->sdram_mode * note: caslat must also be programmed into ddr->sdram_mode
* register. * register.
@ -295,7 +332,11 @@ long int spd_sdram()
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
#ifdef CONFIG_MPC834x
((caslat_83xx & 0x07) << 16 ) |
#else
((caslat_ctrl & 0x07) << 16 ) | ((caslat_ctrl & 0x07) << 16 ) |
#endif
(((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) | (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
( 0x300 ) | ( 0x300 ) |
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);