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ARM: Fix for broken compilation when defining CONFIG_CMD_ELF

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caused by missing dcache status/enable/disable functions.

Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
This commit is contained in:
Hugo Villeneuve 2008-07-10 10:46:33 -04:00 committed by Wolfgang Denk
parent 068c1b77c8
commit c15947d6ce
2 changed files with 40 additions and 12 deletions
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51
cpu/arm926ejs/cpu.c
View File

@ -134,25 +134,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0); return (0);
} }
void icache_enable (void) /* cache_bit must be either C1_IC or C1_DC */
static void cache_enable(uint32_t cache_bit)
{ {
ulong reg; uint32_t reg;
reg = read_p15_c1 (); /* get control reg. */ reg = read_p15_c1(); /* get control reg. */
cp_delay (); cp_delay();
write_p15_c1 (reg | C1_IC); write_p15_c1(reg | cache_bit);
} }
void icache_disable (void) /* cache_bit must be either C1_IC or C1_DC */
static void cache_disable(uint32_t cache_bit)
{ {
ulong reg; uint32_t reg;
reg = read_p15_c1 (); reg = read_p15_c1();
cp_delay (); cp_delay();
write_p15_c1 (reg & ~C1_IC); write_p15_c1(reg & ~cache_bit);
} }
int icache_status (void) void icache_enable(void)
{ {
return (read_p15_c1 () & C1_IC) != 0; cache_enable(C1_IC);
}
void icache_disable(void)
{
cache_disable(C1_IC);
}
int icache_status(void)
{
return (read_p15_c1() & C1_IC) != 0;
}
void dcache_enable(void)
{
cache_enable(C1_DC);
}
void dcache_disable(void)
{
cache_disable(C1_DC);
}
int dcache_status(void)
{
return (read_p15_c1() & C1_DC) != 0;
} }

1
include/configs/davinci_sffsdr.h
View File

@ -137,6 +137,7 @@
#define CONFIG_CMD_SAVES #define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND #define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM #define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
#undef CONFIG_CMD_BDI #undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA #undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_SETGETDCR