minix/u-boot
1
0
Fork 0
mirror of https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git synced 2025-09-10 12:39:22 -04:00
Code Issues Packages Projects Releases Wiki Activity

MIPS: don't use camel-case style

Browse Source 
Replace camel-case style with upper-case style globally.

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
This commit is contained in:
Zhi-zhou Zhang 2012-10-16 15:02:08 +02:00 committed by Daniel Schwierzeck
parent bd23b22bad
commit cb0a6a1ecc
6 changed files with 59 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/mips/cpu/mips32/cache.S
View File

@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */ /* clear tag to invalidate */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_I t0 1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
/* fill once, so data field parity is correct */ /* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
2: cache_op Fill t0 2: cache_op FILL t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 2b bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */ /* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_I t0 1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
9: jr ra 9: jr ra
@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */ /* clear all tags */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1 PTR_ADDU t1, t0, a1
1: cache_op Index_Store_Tag_D t0 1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
/* load from each line (in cached space) */ /* load from each line (in cached space) */
@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b bne t0, t1, 2b
/* clear all tags */ /* clear all tags */
PTR_LI t0, INDEX_BASE PTR_LI t0, INDEX_BASE
1: cache_op Index_Store_Tag_D t0 1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2 PTR_ADDU t0, a2
bne t0, t1, 1b bne t0, t1, 1b
9: jr ra 9: jr ra

8
arch/mips/cpu/mips32/cpu.c
View File

@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return; return;
while (1) { while (1) {
cache_op(Hit_Writeback_Inv_D, addr); cache_op(HIT_WRITEBACK_INV_D, addr);
cache_op(Hit_Invalidate_I, addr); cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend) if (addr == aend)
break; break;
addr += lsize; addr += lsize;
@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) { while (1) {
cache_op(Hit_Writeback_Inv_D, addr); cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend) if (addr == aend)
break; break;
addr += lsize; addr += lsize;
@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) { while (1) {
cache_op(Hit_Invalidate_D, addr); cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend) if (addr == aend)
break; break;
addr += lsize; addr += lsize;

12
arch/mips/cpu/xburst/cpu.c
View File

@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) { for (; addr <= aend; addr += lsize) {
cache_op(Hit_Writeback_Inv_D, addr); cache_op(HIT_WRITEBACK_INV_D, addr);
cache_op(Hit_Invalidate_I, addr); cache_op(HIT_INVALIDATE_I, addr);
} }
} }
@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) for (; addr <= aend; addr += lsize)
cache_op(Hit_Writeback_Inv_D, addr); cache_op(HIT_WRITEBACK_INV_D, addr);
} }
void invalidate_dcache_range(ulong start_addr, ulong stop) void invalidate_dcache_range(ulong start_addr, ulong stop)
@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) for (; addr <= aend; addr += lsize)
cache_op(Hit_Invalidate_D, addr); cache_op(HIT_INVALIDATE_D, addr);
} }
void flush_icache_all(void) void flush_icache_all(void)
@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) { addr += CONFIG_SYS_CACHELINE_SIZE) {
cache_op(Index_Store_Tag_I, addr); cache_op(INDEX_STORE_TAG_I, addr);
} }
/* invalidate btb */ /* invalidate btb */
@ -139,7 +139,7 @@ void flush_dcache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) { addr += CONFIG_SYS_CACHELINE_SIZE) {
cache_op(Index_Writeback_Inv_D, addr); cache_op(INDEX_WRITEBACK_INV_D, addr);
} }
__asm__ __volatile__("sync"); __asm__ __volatile__("sync");

4
arch/mips/cpu/xburst/start.S
View File

@ -96,7 +96,7 @@ relocate_code:
li t0, KSEG0 li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2: 2:
cache Index_Writeback_Inv_D, 0(t0) cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE addi t0, CONFIG_SYS_CACHELINE_SIZE
@ -106,7 +106,7 @@ relocate_code:
li t0, KSEG0 li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3: 3:
cache Index_Invalidate_I, 0(t0) cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE addi t0, CONFIG_SYS_CACHELINE_SIZE

2
arch/mips/include/asm/asm.h
View File

@ -401,7 +401,7 @@ symbol = value
#ifdef CONFIG_SGI_IP28 #ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */ /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h> #include <asm/cacheops.h>
#define R10KCBARRIER(addr) cache Cache_Barrier, addr; #define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else #else
#define R10KCBARRIER(addr) #define R10KCBARRIER(addr)
#endif #endif

82
arch/mips/include/asm/cacheops.h
View File

@ -14,54 +14,54 @@
/* /*
* Cache Operations available on all MIPS processors with R4000-style caches * Cache Operations available on all MIPS processors with R4000-style caches
*/ */
#define Index_Invalidate_I 0x00 #define INDEX_INVALIDATE_I 0x00
#define Index_Writeback_Inv_D 0x01 #define INDEX_WRITEBACK_INV_D 0x01
#define Index_Load_Tag_I 0x04 #define INDEX_LOAD_TAG_I 0x04
#define Index_Load_Tag_D 0x05 #define INDEX_LOAD_TAG_D 0x05
#define Index_Store_Tag_I 0x08 #define INDEX_STORE_TAG_I 0x08
#define Index_Store_Tag_D 0x09 #define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2) #if defined(CONFIG_CPU_LOONGSON2)
#define Hit_Invalidate_I 0x00 #define HIT_INVALIDATE_I 0x00
#else #else
#define Hit_Invalidate_I 0x10 #define HIT_INVALIDATE_I 0x10
#endif #endif
#define Hit_Invalidate_D 0x11 #define HIT_INVALIDATE_D 0x11
#define Hit_Writeback_Inv_D 0x15 #define HIT_WRITEBACK_INV_D 0x15
/* /*
* R4000-specific cacheops * R4000-specific cacheops
*/ */
#define Create_Dirty_Excl_D 0x0d #define CREATE_DIRTY_EXCL_D 0x0d
#define Fill 0x14 #define FILL 0x14
#define Hit_Writeback_I 0x18 #define HIT_WRITEBACK_I 0x18
#define Hit_Writeback_D 0x19 #define HIT_WRITEBACK_D 0x19
/* /*
* R4000SC and R4400SC-specific cacheops * R4000SC and R4400SC-specific cacheops
*/ */
#define Index_Invalidate_SI 0x02 #define INDEX_INVALIDATE_SI 0x02
#define Index_Writeback_Inv_SD 0x03 #define INDEX_WRITEBACK_INV_SD 0x03
#define Index_Load_Tag_SI 0x06 #define INDEX_LOAD_TAG_SI 0x06
#define Index_Load_Tag_SD 0x07 #define INDEX_LOAD_TAG_SD 0x07
#define Index_Store_Tag_SI 0x0A #define INDEX_STORE_TAG_SI 0x0A
#define Index_Store_Tag_SD 0x0B #define INDEX_STORE_TAG_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f #define CREATE_DIRTY_EXCL_SD 0x0f
#define Hit_Invalidate_SI 0x12 #define HIT_INVALIDATE_SI 0x12
#define Hit_Invalidate_SD 0x13 #define HIT_INVALIDATE_SD 0x13
#define Hit_Writeback_Inv_SD 0x17 #define HIT_WRITEBACK_INV_SD 0x17
#define Hit_Writeback_SD 0x1b #define HIT_WRITEBACK_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e #define HIT_SET_VIRTUAL_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f #define HIT_SET_VIRTUAL_SD 0x1f
/* /*
* R5000-specific cacheops * R5000-specific cacheops
*/ */
#define R5K_Page_Invalidate_S 0x17 #define R5K_PAGE_INVALIDATE_S 0x17
/* /*
* RM7000-specific cacheops * RM7000-specific cacheops
*/ */
#define Page_Invalidate_T 0x16 #define PAGE_INVALIDATE_T 0x16
/* /*
* R10000-specific cacheops * R10000-specific cacheops
@ -69,17 +69,17 @@
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops. * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/ */
#define Index_Writeback_Inv_S 0x03 #define INDEX_WRITEBACK_INV_S 0x03
#define Index_Load_Tag_S 0x07 #define INDEX_LOAD_TAG_S 0x07
#define Index_Store_Tag_S 0x0B #define INDEX_STORE_TAG_S 0x0B
#define Hit_Invalidate_S 0x13 #define HIT_INVALIDATE_S 0x13
#define Cache_Barrier 0x14 #define CACHE_BARRIER 0x14
#define Hit_Writeback_Inv_S 0x17 #define HIT_WRITEBACK_INV_S 0x17
#define Index_Load_Data_I 0x18 #define INDEX_LOAD_DATA_I 0x18
#define Index_Load_Data_D 0x19 #define INDEX_LOAD_DATA_D 0x19
#define Index_Load_Data_S 0x1b #define INDEX_LOAD_DATA_S 0x1b
#define Index_Store_Data_I 0x1c #define INDEX_STORE_DATA_I 0x1c
#define Index_Store_Data_D 0x1d #define INDEX_STORE_DATA_D 0x1d
#define Index_Store_Data_S 0x1f #define INDEX_STORE_DATA_S 0x1f
#endif /* __ASM_CACHEOPS_H */ #endif /* __ASM_CACHEOPS_H */