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mx6: Fix reset cause for Power On Reset case

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After booting mx6qsabrelite from POR the following is reported:

CPU:   Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset

This is because both the POR and WDOG bits are set after reset.

Fix this by also checking both bits in the POR case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2012-03-13 07:26:48 +00:00 committed by Stefano Babic
parent c338f0b5c6
commit cece262209
1 changed files with 1 additions and 0 deletions
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arch/arm/cpu/armv7/imx-common/cpu.c
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@ -44,6 +44,7 @@ static char *get_reset_cause(void)
switch (cause) { switch (cause) {
case 0x00001: case 0x00001:
case 0x00011:
return "POR"; return "POR";
case 0x00004: case 0x00004:
return "CSU"; return "CSU";